# US 12,191,769 B2 · Current mode controller and corresponding method of operation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,191,769 B2 - Document ID: US12191769B2 - Status: Granted - Kind: B2 - Application number: 17/961,966 - Filed: 2022-10-07 - Published: 2024-04-18 - Granted: 2025-01-07 - Earliest claimed: 2022-10-07 - Assignees: Infineon Technologies Austria AG - Applicants: Infineon Technologies Austria AG - Inventors: Percy Neyra - Web page: https://patentgrep.com/patent/US12191769B2 ## CPC - H02M 3/158: including plural semiconductor devices as final control devices for a single load - H02M 1/0009: {Devices or circuits for detecting current in a converter} - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) ## Abstract A current mode controller includes: an error amplifier configured to generate an error signal that corresponds to the difference between a reference voltage and a voltage indicative of an output voltage of a power converter; a first current measurement circuit configured to measure current flowing in a high-side switch device of the power converter; a second current measurement circuit configured to measure current flowing in a low-side switch device of the power converter; a comparator configured to indicate when a voltage derived by the first current measurement circuit exceeds the error signal in a peak current control mode, and when a voltage derived by the second current measurement circuit drops below the error signal in a valley current control mode; and circuitry configured to configure the comparator in either the peak current control mode or the valley current control mode for each switching cycle of the power converter. ## Claims ### Claim 1 A current mode controller, comprising: an error amplifier configured to generate an error signal that corresponds to the difference between a reference voltage and a voltage indicative of an output voltage of a power converter; a first current measurement circuit configured to measure current flowing in a high-side switch device of the power converter; a second current measurement circuit configured to measure current flowing in a low-side switch device of the power converter; a comparator configured to indicate when a voltage derived by the first current measurement circuit exceeds the error signal in a peak current control mode, and when a voltage derived by the second current measurement circuit drops below the error signal in a valley current control mode; and circuitry configured to configure the comparator in either the peak current control mode or the valley current control mode for each switching cycle of the power converter. ### Claim 2 (depends on 1) The current mode controller of claim 1, wherein the circuitry comprises: a first switch configured to connect the voltage derived by the first current measurement circuit to a positive input of the comparator in the peak current control mode and a second switch configured to connect the error signal to a negative input of the comparator in the peak current control mode; and a third switch configured to connect the error signal to the positive input of the comparator in the valley current control mode and a fourth switch configured to connect the voltage derived by the second current measurement circuit to the negative input of the comparator in the valley current control mode. ### Claim 3 (depends on 1) The current mode controller of claim 1, wherein the circuitry comprises: a first pulse generator configured to generate a first periodic pulse synched to a system clock generated by the current mode controller and having a predetermined width; a second pulse generator configured to generate a second periodic pulse synched to the system clock and having a variable width that corresponds to a duty cycle of the power converter; and a phase detector configured to determine whether a rising or falling edge of the second periodic pulse lags or leads the corresponding rising or falling edge of the first periodic pulse. ### Claim 4 (depends on 3) The current mode controller of claim 3, wherein the second pulse generator is configured to determine the variable width of the second periodic pulse based on a difference between and an input voltage of the power converter and the voltage indicative of the output voltage of the power converter. ### Claim 5 (depends on 3) The current mode controller of claim 3, wherein the second pulse generator is configured to determine the variable width of the second periodic pulse based on an input voltage of the power converter and a voltage at a switch node between the high-side switch device and the low-side switch device of the power converter. ### Claim 6 (depends on 3) The current mode controller of claim 3, wherein the circuitry comprises: a latch configured to indicate the peak current control mode if the phase detector indicates the rising or falling edge of the second periodic pulse lags the same rising or falling edge of the first periodic pulse, or indicate the valley current control mode if the phase detector indicates the rising or falling edge of the second periodic pulse leads the same rising or falling edge of the first periodic pulse. ### Claim 7 (depends on 3) The current mode controller of claim 3, wherein the circuitry comprises: a latch configured to output a gate drive signal for the high-side switch device of the power converter; a first multiplexor configured, in the peak current control mode, to clock the latch based on the system clock and reset the latch based on an output of the comparator; and a second multiplexor configured, in the valley current control mode, to clock the latch based on the output of the comparator and reset the latch based on the second periodic pulse. ### Claim 8 (depends on 3) The current mode controller of claim 3, wherein the circuitry comprises: a latch configured to output a gate drive signal for the high-side switch device of the power converter; a first multiplexor having the system clock as a first input, an output of the comparator as a second input, a select line controlled by the peak current control mode, and an output that forms a clock input of the latch; and a second multiplexor having the output of the comparator as a first input, the second periodic pulse as a second input, a select line determined by the valley current control mode, and an output that forms a reset input of the latch. ### Claim 9 (depends on 1) The current mode controller of claim 1, wherein the circuitry comprises: a voltage offset circuit configured to inject a voltage offset into the voltage derived by the first current measurement circuit and/or the second current measurement circuit, wherein the voltage offset corresponds to output current ripple of the power converter. ### Claim 10 (depends on 1) The current mode controller of claim 1, wherein the circuitry comprises: a first pulse generator configured to generate a first periodic pulse synched to a system clock generated by the current mode controller and having a constant width; and a phase detector configured to determine whether a rising or falling edge of the voltage at the switch node lags or leads the same rising or falling edge of the first periodic pulse. ### Claim 11 (depends on 10) The current mode controller of claim 10, wherein the circuitry comprises: a first latch having a lagging indicator generated by the phase detector as a clock input and a leading indicator generated by the phase detector as a reset input; and a second latch having the leading indicator generated by the phase detector as a clock input and the lagging indicator generated by the phase detector as a reset input. ### Claim 12 (depends on 11) The current mode controller of claim 11, wherein the circuitry comprises: a second pulse generator configured to generate a second periodic pulse synched to the system clock and having a constant width; a third pulse generator configured to generate a third periodic pulse synched to the system clock and having a constant width; and combinatorial logic configured to determine a transition point from the peak current control mode to the valley current control mode or from the valley current control mode to the peak current control mode, based on the second periodic pulse, the third periodic pulse, the leading indicator generated by the phase detector, the lagging indicator generated by the phase detector, an output of the first latch, and an output of the second latch. ### Claim 13 (depends on 12) The current mode controller of claim 12, wherein the constant width of the first periodic pulse determines the transition point. ### Claim 14 (depends on 12) The current mode controller of claim 12, wherein when transitioning from the peak current control mode to the valley current control mode, the combinatorial logic is configured to terminate early a demagnetizing cycle of a switching period in the peak current control mode and initiate a new magnetizing cycle during the part of the switching period in which the demagnetizing cycle was terminated early. ### Claim 15 (depends on 14) The current mode controller of claim 14, wherein the constant width of the second periodic pulse determines how early the demagnetizing cycle of the switching period in the peak current control mode is terminated. ### Claim 16 (depends on 12) The current mode controller of claim 12, wherein when transitioning from the valley current control mode to the peak current control mode, the combinatorial logic is configured to extend a demagnetizing cycle of a switching period in the valley current control mode such that a subsequent magnetizing cycle that begins at the end of the extended demagnetizing cycle is shortened. ### Claim 17 (depends on 16) The current mode controller of claim 16, wherein the constant width of the third periodic pulse determines how long the demagnetizing cycle of the switching period in the peak current control mode is extended. ### Claim 18 (depends on 12) The current mode controller of claim 12, wherein the constant width of the second periodic pulse is greater than the constant width of the first periodic pulse, and wherein the second periodic pulse and the third periodic pulse have the same constant width. ### Claim 19 (depends on 12) The current mode controller of claim 12, wherein the constant width of the second periodic pulse and the constant width of the third periodic pulse are determined based on the constant width of the first periodic pulse and chosen to cancel disturbances on an average inductor current of the power converter. ### Claim 20 A method of operating a current mode controller, the method comprising: generating an error signal that corresponds to the difference between a reference voltage and a voltage indicative of an output voltage of a power converter; measuring, via a first current measurement circuit, current flowing in a high-side switch device of the power converter; measuring, via a second current measurement circuit, current flowing in a low-side switch device of the power converter; indicating, via a comparator, when a voltage derived by the first current measurement circuit exceeds the error signal in a peak current control mode, and when a voltage derived by the second current measurement circuit drops below the error signal in a valley current control mode; and configuring the comparator in either the peak current control mode or the valley current control mode for each switching cycle of the power converter.