# US 12,191,764 B2 · Charge pump circuit and drive device

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- Number: US 12,191,764 B2
- Document ID: US12191764B2
- Status: Granted
- Kind: B2
- Application number: 18/163,892
- Filed: 2023-02-03
- Published: 2024-03-21
- Granted: 2025-01-07
- Earliest claimed: 2022-09-16
- Assignees: Kabushiki Kaisha Toshiba; Toshiba Devices & Storage Corporation
- Applicants: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation
- Inventors: Mitsumasa Sonoda
- Web page: https://patentgrep.com/patent/US12191764B2

## CPC

- H02M 3/07: using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps}
- H02M 1/38: Means for preventing simultaneous conduction of switches
- H02M 1/08: Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M 1/088: for the simultaneous control of series or parallel connected semiconductor devices
- H02M 3/076: {the clock signals being boosted to a value being higher than the input voltage value}
- H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence)
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A charge pump circuit includes a first capacitor including a first end supplied for a voltage, and a second end; a second capacitor including a third end supplied for a pulse signal, and a fourth end coupled to a node; a third capacitor including a fifth end supplied for the pulse signal, and sixth end; a first transistor including a seventh end coupled to the second end, an eighth end coupled to the node, and a first gate; a second transistor including a ninth end coupled to the first end, a tenth end coupled to the node, and a second gate; and a circuit including a first terminal coupled to the node, a second terminal coupled to the sixth end, a third terminal coupled to the first gate, and a fourth terminal coupled to the second gate.

## Claims

### Claim 1

A charge pump circuit comprising:
a first capacitor including a first end to which a first voltage is supplied;
a second capacitor including a first end to which a first pulse signal is supplied, and a second end coupled to a first node;
a third capacitor including a first end to which the first pulse signal is supplied;
a first transistor including a first end coupled to a second end of the first capacitor, and a second end coupled to the first node;
a second transistor including a first end coupled to the first end of the first capacitor, and a second end coupled to the first node; and
a first circuit including a first input terminal coupled to the first node, a second input terminal coupled to a second end of the third capacitor, a first output terminal coupled to a gate of the first transistor, and a second output terminal coupled to a gate of the second transistor.

### Claim 2 (depends on 1)

The charge pump circuit according to claim 1, wherein
the first circuit includes a first NAND circuit and a first NOR circuit,
the first NAND circuit including:
a first input terminal coupled to the first node;
a second input terminal coupled to the second end of the third capacitor; and
an output terminal coupled to the gate of the first transistor,
the first NOR circuit including:
a first input terminal coupled to the first node;
a second input terminal coupled to the second end of the third capacitor; and
an output terminal coupled to the gate of the second transistor.

### Claim 3 (depends on 1)

The charge pump circuit according to claim 1, wherein
the first transistor is a P-type MOS transistor, and
the second transistor is an N-type MOS transistor.

### Claim 4 (depends on 3)

The charge pump circuit according to claim 3, wherein
the first end of each of the first transistor and the second transistor is a source, and
the second end of each of the first transistor and the second transistor is a drain.

### Claim 5 (depends on 1)

The charge pump circuit according to claim 1, further comprising:
a fourth capacitor including a first end to which a second pulse signal is supplied, and a second end coupled to a second node, the second pulse signal being an inverted signal of the first pulse signal;
a fifth capacitor including a first end to which the second pulse signal is supplied;
a third transistor including a first end coupled to the second end of the first capacitor, and a second end coupled to the second node;
a fourth transistor including a first end coupled to the first end of the first capacitor, and a second end coupled to the second node; and
a second circuit including a first input terminal coupled to the second node, a second input terminal coupled to a second end of the fifth capacitor, a first output terminal coupled to a gate of the third transistor, and a second output terminal coupled to a gate of the fourth transistor.

### Claim 6 (depends on 5)

The charge pump circuit according to claim 5, wherein
the first circuit includes a first NAND circuit and a first NOR circuit,
the first NAND circuit including:
a first input terminal coupled to the first node;
a second input terminal coupled to the second end of the third capacitor; and
an output terminal coupled to the gate of the first transistor,
the first NOR circuit including:
a first input terminal coupled to the first node;
a second input terminal coupled to the second end of the third capacitor; and
an output terminal coupled to the gate of the second transistor, and
the second circuit includes a second NAND circuit and a second NOR circuit,
the second NAND circuit including:
a first input terminal coupled to the second node;
a second input terminal coupled to the second end of the fifth capacitor; and
an output terminal coupled to the gate of the third transistor,
the second NOR circuit including:
a first input terminal coupled to the second node;
a second input terminal coupled to the second end of the fifth capacitor; and
an output terminal coupled to the gate of the fourth transistor.

### Claim 7 (depends on 5)

The charge pump circuit according to claim 5, wherein
the first transistor and the third transistor are P-type MOS transistors, and
the second transistor and the fourth transistor are N-type MOS transistors.

### Claim 8 (depends on 7)

The charge pump circuit according to claim 7, wherein
the first end of each of the first transistor, the second transistor, the third transistor, and the fourth transistor is a source, and
the second end of each of the first transistor, the second transistor, the third transistor, and the fourth transistor is a drain.

### Claim 9

A drive device comprising a charge pump circuit, the charge pump circuit including:
a first capacitor including a first end to which a first voltage is supplied;
a second capacitor including a first end to which a first pulse signal is supplied, and a second end coupled to a first node;
a third capacitor including a first end to which the first pulse signal is supplied;
a first transistor including a first end coupled to a second end of the first capacitor, and a second end coupled to the first node;
a second transistor including a first end coupled to the first end of the first capacitor, and a second end coupled to the first node;
a first circuit including a first input terminal coupled to the first node, a second input terminal coupled to a second end of the third capacitor, a first output terminal coupled to a gate of the first transistor, and a second output terminal coupled to a gate of the second transistor; and
an output terminal coupled to the second end of the first capacitor,
the drive device being configured to drive an external motor based on a voltage of the output terminal.

### Claim 10 (depends on 9)

The drive device according to claim 9, wherein
the first circuit includes a first NAND circuit and a first NOR circuit,
the first NAND circuit including:
a first input terminal coupled to the first node;
a second input terminal coupled to the second end of the third capacitor; and
an output terminal coupled to the gate of the first transistor,
the first NOR circuit including:
a first input terminal coupled to the first node;
a second input terminal coupled to the second end of the third capacitor; and
an output terminal coupled to the gate of the second transistor.

### Claim 11 (depends on 9)

The drive device according to claim 9, wherein
the first transistor is a P-type MOS transistor, and
the second transistor is an N-type MOS transistor.

### Claim 12 (depends on 11)

The drive device according to claim 11, wherein
the first end of each of the first transistor and the second transistor is a source, and
the second end of each of the first transistor and the second transistor is a drain.

### Claim 13 (depends on 9)

The drive device according to claim 9, further comprising:
a fourth capacitor including a first end to which a second pulse signal is supplied, and a second end coupled to a second node, the second pulse signal being an inverted signal of the first pulse signal;
a fifth capacitor including a first end to which the second pulse signal is supplied;
a third transistor including a first end coupled to the second end of the first capacitor, and a second end coupled to the second node;
a fourth transistor including a first end coupled to the first end of the first capacitor, and a second end coupled to the second node; and
a second circuit including a first input terminal coupled to the second node, a second input terminal coupled to a second end of the fifth capacitor, a first output terminal coupled to a gate of the third transistor, and a second output terminal coupled to a gate of the fourth transistor.

### Claim 14 (depends on 13)

The drive device according to claim 13, wherein
the first circuit includes a first NAND circuit and a first NOR circuit,
the first NAND circuit including:
a first input terminal coupled to the first node;
a second input terminal coupled to the second end of the third capacitor; and
an output terminal coupled to the gate of the first transistor,
the first NOR circuit including:
a first input terminal coupled to the first node;
a second input terminal coupled to the second end of the third capacitor; and
an output terminal coupled to the gate of the second transistor, and
the second circuit includes a second NAND circuit and a second NOR circuit,
the second NAND circuit including:
a first input terminal coupled to the second node;
a second input terminal coupled to the second end of the fifth capacitor; and
an output terminal coupled to the gate of the third transistor,
the second NOR circuit including:
a first input terminal coupled to the second node;
a second input terminal coupled to the second end of the fifth capacitor; and
an output terminal coupled to the gate of the fourth transistor.

### Claim 15 (depends on 13)

The drive device according to claim 13, wherein
the first transistor and the third transistor are P-type MOS transistors, and
the second transistor and the fourth transistor are N-type MOS transistors.

### Claim 16 (depends on 15)

The drive device according to claim 15, wherein
the first end of each of the first transistor, the second transistor, the third transistor, and the fourth transistor is a source, and
the second end of each of the first transistor, the second transistor, the third transistor, and the fourth transistor is a drain.