# US 12,191,760 B2 · Pulse width modulation circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,191,760 B2 - Document ID: US12191760B2 - Status: Granted - Kind: B2 - Application number: 18/046,966 - Filed: 2022-10-17 - Published: 2024-04-18 - Granted: 2025-01-07 - Earliest claimed: 2022-10-17 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Huihuang Chen - Web page: https://patentgrep.com/patent/US12191760B2 ## CPC - H02M 1/4208: {Arrangements for improving power factor of AC input} - H02M 1/0012: {Control circuits using digital or numerical techniques (in DC/DC converters H02M3/157, H02M3/33515; in DC-AC converters H02M7/53873)} - H02M 1/08: Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters - H02M 1/4233: {using a bridge converter comprising active switches} - H02M 7/5395: by pulse-width modulation - H03K 7/08: Duration or width modulation {; Duty cycle modulation} - H02M 3/156: with automatic control of output voltage or current, e.g. switching regulators - H02M 3/157: with digital control - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A pulse width modulation (PWM) system includes a PWM circuit and a controller. The PWM circuit includes a counter, a period register, and a duty cycle register. The controller is coupled to the PWM circuit. The controller is configured to calculate a period value and a duty cycle value. The controller is also configured to load the duty cycle value into the duty cycle register responsive to a count value of the counter being equal to a value of the duty cycle register and the duty cycle value being less than the period value. ## Claims ### Claim 1 A pulse width modulation (PWM) system, comprising: a PWM circuit including: a counter; a period register; and a duty cycle register; and a controller coupled to the PWM circuit, the controller configured to: calculate a period value and a duty cycle value; and load the duty cycle value into the duty cycle register responsive to a count value of the counter being equal to a value of the duty cycle register, and the duty cycle value being less than the period value. ### Claim 2 (depends on 1) The PWM system of claim 1, wherein the controller is configured to: responsive to the duty cycle value being less than the period value, enable generation of an interrupt triggered by the count value of the counter being equal to the value of the duty cycle register; and load the duty cycle value into the duty cycle register responsive to the interrupt. ### Claim 3 (depends on 2) The PWM system of claim 2, wherein the controller is configured to enable generation of the interrupt responsive to a current value of the duty cycle register being greater than or equal to a current value of the period register. ### Claim 4 (depends on 2) The PWM system of claim 2, wherein the controller is configured to disable the interrupt responsive to loading duty cycle value into the duty cycle register. ### Claim 5 (depends on 2) The PWM system of claim 2, wherein the controller is configured to: load the duty cycle value into the duty cycle register using an immediate mode; and after loading the duty cycle value into the duty cycle register, set the duty cycle register to operate in a shadow mode. ### Claim 6 (depends on 1) The PWM system of claim 1, wherein the controller is configured to: responsive to the duty cycle value being greater than or equal to the period value, load the duty cycle value into the duty cycle register. ### Claim 7 (depends on 1) The PWM system of claim 1, wherein: the PWM circuit is a first PWM circuit; and the PWM system includes a second PWM circuit having: a counter; and the controller is configured to load the duty cycle value into the duty cycle register responsive to the value of the counter of the second PWM circuit being equal to zero. ### Claim 8 A method for pulse width modulation (PWM), comprising: by a controller coupled to a PWM circuit: calculating a period value and a duty cycle value for use in the PWM circuit; determining that the duty cycle value is less than the period value; determining that a count value of a counter of the PWM circuit is equal to a value of a duty cycle register of the PWM circuit; and loading the duty cycle value into the duty cycle register responsive to the count value being equal to the value of the duty cycle register, and the duty cycle value being less than the period value. ### Claim 9 (depends on 8) The method of claim 8 further comprising: responsive to the duty cycle value being less than the period value, enabling, by the controller, generation of an interrupt triggered by the count value being equal to the value of the duty cycle register; and loading, by the controller, the duty cycle value into the duty cycle register responsive to the interrupt. ### Claim 10 (depends on 9) The method of claim 9 further comprising: enabling, by the controller, generation of the interrupt responsive to a current value of the duty cycle register being greater than or equal to a current value of a period register; and disabling, by the controller, generation of the interrupt responsive to loading the duty cycle register. ### Claim 11 (depends on 9) The method of claim 9 further comprising: loading, by the controller, the duty cycle value into the duty cycle register using an immediate mode; and after loading the duty cycle value into the duty cycle register, setting, by the controller, the duty cycle register to operate in a shadow mode. ### Claim 12 (depends on 8) The method of claim 8 further comprising: responsive to the duty cycle value being greater than or equal to the period value, loading, by the controller, the duty cycle value into the duty cycle register. ### Claim 13 (depends on 8) The method of claim 8 wherein: the PWM circuit is a first PWM circuit; and the method includes: loading, by the controller, the duty cycle value into the duty cycle register responsive to the value of a counter of a second PWM circuit being zero. ### Claim 14 A non-transient computer-readable medium encoded with instructions that when executed cause a processor to: calculate a period value and a duty cycle value for use in a pulse width modulation (PWM) circuit; determine that the duty cycle value is less than the period value; determine that a count value of a counter of the PWM circuit is equal to a value of a duty cycle register of the PWM circuit; and load the duty cycle value into the duty cycle register responsive to the count value being equal to the value of the duty cycle register, and the duty cycle value being less than the period value. ### Claim 15 (depends on 14) The non-transient computer-readable medium of claim 14, wherein the instructions, when executed, cause the processor to: responsive to the duty cycle value being less than the period value, enable generation of an interrupt triggered by the count value being equal to the value of the duty cycle register; and load the duty cycle value into the duty cycle register responsive to the interrupt. ### Claim 16 (depends on 15) The non-transient computer-readable medium of claim 15, wherein the instructions, when executed, cause the processor to: enable generation of the interrupt responsive to a current value of the duty cycle register being greater than or equal to a current value of a period register; and disable generation of the interrupt responsive to loading the duty cycle register. ### Claim 17 (depends on 15) The non-transient computer-readable medium of claim 15, wherein the instructions, when executed, cause the processor to: load the duty cycle value into the duty cycle register using an immediate mode; and after loading the duty cycle value into the duty cycle register, set the duty cycle register to operate in a shadow mode. ### Claim 18 (depends on 14) The non-transient computer-readable medium of claim 14, wherein the instructions, when executed, cause the processor to: responsive to the duty cycle value being greater than or equal to the period value, load the duty cycle value into the duty cycle register. ### Claim 19 (depends on 14) The non-transient computer-readable medium of claim 14, wherein: the PWM circuit is a first PWM circuit; and the instructions, when executed, cause the processor to: load the duty cycle value into the duty cycle register responsive to the value of a counter of a second PWM circuit being equal to zero. ### Claim 20 A power factor correction (PFC) circuit, comprising: a half-bridge circuit, including a high-side transistor and a low-side transistor; a pulse width modulation (PWM) system including: a PWM circuit having: a first output coupled to the high-side transistor; a second output coupled to the low-side transistor; a counter; a period register; and a duty cycle register; and a controller coupled to the PWM circuit, the controller configured to: calculate a period value and a duty cycle value; and load the duty cycle value into the duty cycle register responsive to a count value of the counter being equal to a value of the duty cycle register, and the duty cycle value being less than the period value. ### Claim 21 (depends on 20) The PFC circuit of claim 20, wherein the controller is configured to: responsive to the duty cycle value being less than the period value, enable generation of an interrupt triggered by the count value of the counter being equal to the value of the duty cycle register; and load the duty cycle value into the duty cycle register responsive to the interrupt. ### Claim 22 (depends on 21) The PFC circuit of claim 21, wherein the controller is configured to: enable generation of the interrupt responsive to a current value of the duty cycle register being greater than or equal to a current value of the period register; disable the interrupt responsive to loading the duty cycle register; load the duty cycle value into the duty cycle register using an immediate mode; and after loading the duty cycle value into the duty cycle register, set the duty cycle register to operate in a shadow mode. ### Claim 23 (depends on 20) The PFC circuit of claim 20, wherein the controller is configured to: responsive to the duty cycle value being greater than or equal to the period value, load the duty cycle value into the duty cycle register. ### Claim 24 (depends on 20) The PFC circuit of claim 20, wherein: the PWM circuit is a first PWM circuit; and the PWM system includes a second PWM circuit having: a counter; and the controller is configured to load the duty cycle register responsive to the value of the counter of the second PWM circuit being zero.