# US 12,191,411 B2 · Semiconductor substrate, solar cell, and photovoltaic module > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,191,411 B2 - Document ID: US12191411B2 - Status: Granted - Kind: B2 - Application number: 17/872,035 - Filed: 2022-07-25 - Published: 2023-12-21 - Granted: 2025-01-07 - Earliest claimed: 2022-06-21 - Assignees: Zhejiang Jinko Solar Co., Ltd.; Jinko Solar Co., Ltd. - Applicants: Zhejiang Jinko Solar Co., Ltd.; Jinko Solar Co., Ltd. - Inventors: Huimin Li; Menglei Xu; Jie Yang; Xinyu Zhang - Web page: https://patentgrep.com/patent/US12191411B2 ## CPC - H10F 77/703: {of the semiconductor bodies, e.g. textured active layers} - H10F 77/707: {of the substrates or of layers on substrates, e.g. textured ITO layer on a glass substrate} - H10F 10/146: {Back-junction photovoltaic cells, e.g. having interdigitated base-emitter regions on the back side} - H10F 10/166: the Group IV-IV heterojunctions being heterojunctions of crystalline and amorphous materials, e.g. silicon heterojunction [SHJ] photovoltaic cells - H10F 19/908: {for back-contact photovoltaic cells} - H10F 71/121: {The active layers comprising only Group IV materials} - H10F 77/148: {Shapes of potential barriers} - H10F 77/1642: {including only Group IV materials} - H10F 77/315: {the coatings being antireflective or having enhancing optical properties} - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION ## Abstract A semiconductor substrate, including a back surface having N-type conductive regions and P-type conductive regions. The N-type conductive regions are provided with first non-pyramidal texture structures, and the P-type conductive regions are provided with second non-pyramidal texture structures. A top surface of the first non-pyramidal texture structure is a polygonal plane, and a top surface of the second non-pyramidal texture structure is a polygonal plane. A one-dimensional size of the top surface of the first non-pyramidal texture structure is less than a one-dimensional size of the top surface of the second non-pyramidal texture structure. The one-dimensional size of the top surface of the first non-pyramidal texture structure is in a range of 5 μm to 12 μm. The one-dimensional size of the top surface of the second non-pyramidal texture structure is in a range of 10 μm to 40 μm. ## Claims ### Claim 1 A semiconductor substrate, comprising: a back surface including N-type conductive regions and P-type conductive regions formed thereon, wherein the N-type conductive regions are provided with first non-pyramidal texture structures, and the P-type conductive regions are provided with second non-pyramidal texture structures; and each of the first non-pyramidal texture structures and the second non-pyramidal texture structures is formed as a shape resulting from destruction of a spire of a pyramidal microstructure that protrudes towards a direction away from the back surface of the semiconductor substrate; a top surface of the first non-pyramidal texture structure is a polygonal plane and a top surface of the second non-pyramidal texture structure is a polygonal plane, and a one-dimensional size of the top surface of the first non-pyramidal texture structure in a dimension is less than a one-dimensional size of the top surface of the second non-pyramidal texture structure in the same dimension, the one-dimensional size being a length, a width, a diagonal length, or a circular diameter of the top surface; and the one-dimensional size of the top surface of the first non-pyramidal texture structure is greater than or equal to 5 μm and less than or equal to 12 μm; and the one-dimensional size of the top surface of the second non-pyramidal texture structure is greater than or equal to 10 μm and less than or equal to 40 μm. ### Claim 2 (depends on 1) The semiconductor substrate according to claim 1, wherein the one-dimensional size of the top surface of the first non-pyramidal texture structure is greater than or equal to 7 μm and less than or equal to 10 μm. ### Claim 3 (depends on 1) The semiconductor substrate according to claim 1, wherein the one- dimensional size of the top surface of the second non-pyramidal texture structure is greater than or equal to 15 μm and less than or equal to 35 μm. ### Claim 4 (depends on 1) The semiconductor substrate according to claim 1, wherein the first non-pyramidal texture structure comprises: two or more first substructures that are at least partially stacked on one another, and a one-dimensional size of a top surface of the outermost first substructure is greater than or equal to 5 μm and less than or equal to 12 μm, in a direction away from the back surface and perpendicular to the back surface; and two or more second substructures that are adjacent but not stacked on one another, and a one-dimensional size of a top surface of the second substructure away from the back surface is greater than or equal to 5 μm and less than or equal to 12 μm. ### Claim 5 (depends on 1) The semiconductor substrate according to claim 1, wherein the second non-pyramidal texture structure comprises: two or more third substructures that are at least partially stacked on one another, and a one-dimensional size of a top surface of the outermost third substructure is greater than or equal to 10 μm and less than or equal to 40 μm, in a direction away from the back surface and perpendicular to the back surface; and two or more fourth substructures that are adjacent but not stacked on one another, and a one-dimensional size of a top surface of the fourth substructure away from the back surface is greater than or equal to 10 μm and less than or equal to 40 μm. ### Claim 6 (depends on 1) The semiconductor substrate according to claim 1, wherein a dividing line is provided between the N-type conductive region and the P-type conductive region, and the N-type conductive region and/or the P-type conductive region are provided with holes close to the dividing line. ### Claim 7 (depends on 6) The semiconductor substrate according to claim 6, wherein the N-type conductive region and/or the P-type conductive region are provided with the holes having a distance of 5 μm to 15 μm away from the dividing line. ### Claim 8 (depends on 7) The semiconductor substrate according to claim 7, wherein the N-type conductive region and/or the P-type conductive region are provided with the holes having a distance of 5 μm to 10 μm away from the dividing line. ### Claim 9 (depends on 6) The semiconductor substrate according to claim 6, wherein a diameter of the hole ranges from 1 μm to 10 μm. ### Claim 10 (depends on 9) The semiconductor substrate according to claim 9, wherein the diameter of the hole ranges from 1 μm to 5 μm. ### Claim 11 (depends on 6) The semiconductor substrate according to claim 6, wherein a depth of the hole ranges from 0.5 μm to 2 μm. ### Claim 12 (depends on 6) The semiconductor substrate according to claim 6, wherein a gap between two adjacent N-type conductive regions or between two adjacent P-type conductive regions ranges from 0.8 mm to 1.2 mm; the N-type conductive regions distributed on the back surface of the semiconductor substrate account for 50% to 85% of the back surface; and the P-type conductive regions distributed on the back surface of the semiconductor substrate account for 15% to 50% of the back surface. ### Claim 13 (depends on 1) The semiconductor substrate according to claim 1, wherein a shape of the polygonal plane includes at least one of a rhombus, a square, a trapezoid, an approximate rhombus, an approximate square, or an approximate trapezoid. ### Claim 14 (depends on 1) The semiconductor substrate according to claim 1, wherein the semiconductor substrate is a P-type crystalline silicon substrate. ### Claim 15 A solar cell, comprising: a semiconductor substrate, including: a back surface including N-type conductive regions and P-type conductive regions formed thereon, wherein the N-type conductive regions are provided with first non-pyramidal texture structures, and the P-type conductive regions are provided with second non-pyramidal texture structures; and each of the first non-pyramidal texture structures and the second non-pyramidal texture structures is formed as a shape resulting from destruction of a spire of a pyramidal microstructure that protrudes towards a direction away from the back surface of the semiconductor substrate; a top surface of the first non-pyramidal texture structure is a polygonal plane and a top surface of the second non-pyramidal texture structure is a polygonal plane, and a one-dimensional size of the top surface of the first non-pyramidal texture structure in a dimension is less than a one-dimensional size of the top surface of the second non-pyramidal texture structure in the same dimension, the one-dimensional size being a length, a width, a diagonal length, or a circular diameter of the top surface; and the one-dimensional size of the top surface of the first non-pyramidal texture structure is greater than or equal to 5 μm and less than or equal to 12 μm; and the one-dimensional size of the top surface of the second non-pyramidal texture structure is greater than or equal to 10 μm and less than or equal to 40 μm; a tunnel oxide layer formed over the N-type conductive region; a local back surface field formed in the P-type conductive region; a polysilicon film layer formed over a side of the tunnel oxide layer facing away from the semiconductor substrate; an eutectic layer formed in the local back surface field; a back-surface passivation layer formed over a side of the polysilicon film layer facing away from the tunnel oxide layer and over the P-type conductive region; a first electrode passing through the back-surface passivation layer to form ohmic contact with the local back surface field; and a second electrode passing through the back-surface passivation layer to form ohmic contact with the polysilicon film layer. ### Claim 16 (depends on 15) The solar cell according to claim 15, further comprising: a front-surface passivation layer and an antireflection layer formed over a front surface of the semiconductor substrate and sequentially stacked in a direction away from the semiconductor substrate. ### Claim 17 (depends on 15) The solar cell according to claim 15, wherein the one-dimensional size of the top surface of the first non-pyramidal texture structure is greater than or equal to 7 μm and less than or equal to 10 μm. ### Claim 18 (depends on 15) The solar cell according to claim 15, wherein the one-dimensional size of the top surface of the second non-pyramidal texture structure is greater than or equal to 15 μm and less than or equal to 35 μm. ### Claim 19 (depends on 15) The solar cell according to claim 15, wherein a dividing line is provided between the N-type conductive region and the P-type conductive region, and the N-type conductive region and/or the P-type conductive region are provided with holes close to the dividing line. ### Claim 20 A photovoltaic module, comprising: a plurality of solar cells electrically connected into a solar cell string in a form of an entire cell or multiple-cut cells, wherein at least one of the plurality of solar cells includes: a semiconductor substrate, including: a back surface including N-type conductive regions and P-type conductive regions formed thereon, wherein the N-type conductive regions are provided with first non-pyramidal texture structures, and the P-type conductive regions are provided with second non-pyramidal texture structures; and each of the first non-pyramidal texture structures and the second non-pyramidal texture structures is formed as a shape resulting from destruction of a spire of a pyramidal microstructure that protrudes towards a direction away from the back surface of the semiconductor substrate; a top surface of the first non-pyramidal texture structure is a polygonal plane and a top surface of the second non-pyramidal texture structure is a polygonal plane, and a one-dimensional size of the top surface of the first non-pyramidal texture structure in a dimension is less than a one-dimensional size of the top surface of the second non-pyramidal texture structure in the same dimension, the one-dimensional size being a length, a width, a diagonal length, or a circular diameter of the top surface; and the one-dimensional size of the top surface of the first non-pyramidal texture structure is greater than or equal to 5 μm and less than or equal to 12 μm; and the one-dimensional size of the top surface of the second non-pyramidal texture structure is greater than or equal to 10 μm and less than or equal to 40 μm; a tunnel oxide layer formed over the N-type conductive region; a local back surface field formed in the P-type conductive region; a polysilicon film layer formed over a side of the tunnel oxide layer facing away from the semiconductor substrate; an eutectic layer formed in the local back surface field; a back-surface passivation layer formed over a side of the polysilicon film layer facing away from the tunnel oxide layer and over the P-type conductive region; a first electrode passing through the back-surface passivation layer to form ohmic contact with the local back surface field; and a second electrode passing through the back-surface passivation layer to form ohmic contact with the polysilicon film layer.