# US 12,191,401 B2 · Manufacturing method for semiconductor structure having a plurality of fins > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,191,401 B2 - Document ID: US12191401B2 - Status: Granted - Kind: B2 - Application number: 18/415,702 - Filed: 2024-01-18 - Published: 2024-06-13 - Granted: 2025-01-07 - Earliest claimed: 2021-06-25 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company Ltd. - Inventors: Chia-Ming Hsu; Yi-Jing Li; Chih-Hsin Ko; Kuang-Hsin Chen; Da-Wen Lin; Clement Hsingjen Wann - Web page: https://patentgrep.com/patent/US12191401B2 ## CPC - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 30/031: {of thin-film transistors [TFT]} - H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around} - H10D 62/118: {Nanostructure semiconductor bodies} - H10D 62/121: {oriented parallel to substrates} - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10P 14/3411: {Silicon, silicon germanium or germanium} - H10P 14/3452: {Microstructure} - B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic - H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES ## Abstract Present disclosure provides a method including: forming a semiconductor stack having at least one SiGe layer; forming a plurality of fins from the semiconductor stack by a first etching operation, each of the plurality of fins comprising a first portion and a second portion over the first portion, the first portion being separated from the second portion by a SiGe portion; forming a poly gate stripe orthogonally over the plurality of fins; forming a recess on each of the plurality of fins abutting the poly gate; recessing the SiGe portion by a second etching operation through the recess; forming a first spacer and a second spacer to surround the SiGe portion; and removing the SiGe portion. ## Claims ### Claim 1 A method, comprising: forming a semiconductor stack having at least one SiGe layer; forming a plurality of fins from the semiconductor stack by a first etching operation, each of the plurality of fins comprising a first portion and a second portion over the first portion, the first portion being separated from the second portion by a SiGe portion; forming a poly gate stripe orthogonally over the plurality of fins; forming a recess on each of the plurality of fins abutting the poly gate stripe; recessing the SiGe portion by a second etching operation through the recess; forming a first spacer and a second spacer to surround the SiGe portion; and removing the SiGe portion. ### Claim 2 (depends on 1) The method of claim 1, further comprising: forming an insulating region having an upper portion over the second portion and a bottom portion beneath the second portion; and forming a metal gate having an upper portion and a bottom portion, wherein the bottom portion of the metal gate is formed in a space surrounded by the first spacer, the second spacer, the first portion and the bottom portion of the insulating region, and the upper portion of the metal gate is formed over the upper portion of the insulating region. ### Claim 3 (depends on 2) The method of claim 2, wherein a distance between the first portion and the second portion is ranged from about 10 nm to about 20 nm. ### Claim 4 (depends on 1) The method of claim 1, further comprising: forming a first conductive region and a second conductive region, wherein the first conductive region abuts a first lateral surface of the first portion and a first lateral surface of the second portion, and the second conductive region abuts a second lateral surface of the first portion and a second lateral surface of the second portion. ### Claim 5 (depends on 1) The method of claim 1, wherein forming the plurality of fins from the semiconductor stack by the first etching operation comprises: forming a space layer over the semiconductor stack; and performing the first etching operation according to the space layer to forming the plurality of fins and the SiGe portion. ### Claim 6 (depends on 5) The method of claim 5, wherein the SiGe layer is etched using the first etching operation, and the SiGe layer is etched to be the SiGe portion. ### Claim 7 (depends on 1) The method of claim 1, wherein the second portion of each of the plurality of fins is a trapezoid. ### Claim 8 (depends on 1) The method of claim 1, wherein the second portion of each of the plurality of fins is a triangle. ### Claim 9 A method, comprising: forming a semiconductor stack; forming a plurality of fins from the semiconductor stack by a first etching operation, each of the plurality of fins comprising a first portion and a second portion over the first portion, the first portion being separated from the second portion; forming a first spacer and a second spacer, wherein each of the first spacer and the second spacer is in contact with the first portion and the second portion, and the first spacer and the second spacer are separated from each other; and forming a metal gate having an upper portion and a bottom portion, wherein the bottom portion of the metal gate is formed in a space between the first spacer and the second spacer, and the upper portion of the metal gate is formed over the second portion of each of the plurality of fins. ### Claim 10 (depends on 9) The method of claim 9, wherein the semiconductor stack has a plurality of epitaxial layers and at least one SiGe layer, wherein the at least one SiGe layer is sandwiched by two of the plurality of epitaxial layers. ### Claim 11 (depends on 10) The method of claim 10, wherein after the first etch operation, the SiGe layer is etched to be a SiGe portion, wherein the first spacer and the second spacer are formed on and in contact with opposite sides of the SiGe portion. ### Claim 12 (depends on 11) The method of claim 11, further comprising: before forming the first spacer and the second spacer, recessing the SiGe portion to form a space by a second etching operation, wherein the first spacer and the second spacer are formed in space, wherein a side wall of the first spacer is align with a first lateral surface of the second portion, and a side wall of the second spacer is align with a second lateral surface of the second portion. ### Claim 13 (depends on 11) The method of claim 11, further comprising: removing the SiGe portion to form a discontinuous region between the first portion and the second portion before forming the metal gate; and forming an insulating region having an upper portion over the second portion and a bottom portion beneath the second portion, wherein the bottom portion of the insulating region is formed in the discontinuous region, and in contact with the first portion, the second portion, the first spacer, and the second spacer. ### Claim 14 (depends on 13) The method of claim 13, wherein the bottom portion of the metal gate is formed in the bottom portion of the insulation region, wherein the bottom portion of the metal gate is spaced apart from the first portion and the second portion by the bottom portion of the insulation region. ### Claim 15 (depends on 9) The method of claim 9, further comprising: forming a first conductive region and a second conductive region, wherein the first conductive region abuts a first lateral surface of the first portion and a first lateral surface of the second portion, and the second conductive region abuts a second lateral surface of the first portion and a second lateral surface of the second portion. ### Claim 16 A method, comprising: forming a semiconductor fin having a first portion and a second portion over the first portion; forming an insulating region having a bottom portion and an upper portion; and forming a metal gate having a bottom portion and an upper portion, wherein the bottom portion of the insulating region is between the first portion and the second portion, and the upper portion of the metal gate and the upper portion of the insulating region are over the second portion, wherein the bottom portion of the insulating region and the bottom portion of the metal gate are between the first portion and the second portion, the bottom portion of the metal gate is surrounded by the bottom portion of the insulating region, wherein a width of the metal gate is smaller than a width of the second portion. ### Claim 17 (depends on 16) The method of claim 16, wherein the upper portion of the insulating region is between the second portion and the upper portion of the metal gate. ### Claim 18 (depends on 16) The method of claim 16, further comprising: forming a first spacer and a second spacer between the first portion and the second portion, wherein the bottom portion of the insulating region is formed between the first spacer and the second spacer, wherein a side wall of the first spacer is aligned with a first lateral surface of the second portion, and a side wall with a second lateral surface of the second portion. ### Claim 19 (depends on 18) The method of claim 18, further comprising: forming a first conductive region and a second conductive region, wherein the first conductive region abutting the first lateral surface of the second portion and the first spacer, and the second conductive region butting the second lateral surface of the second portion and the second spacer. ### Claim 20 (depends on 19) The method of claim 19, further comprising: forming a first recess and a second recess on the first portion, wherein the first conductive region and the second conductive region are extended into the first recess and the second recess, respectively.