# US 12,191,398 B2 · Semiconductor device comprising lightly doped drain (LDD) region between channel and drain region > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,191,398 B2 - Document ID: US12191398B2 - Status: Granted - Kind: B2 - Application number: 17/579,740 - Filed: 2022-01-20 - Published: 2022-05-12 - Granted: 2025-01-07 - Earliest claimed: 2019-08-30 - Assignees: Japan Display Inc. - Applicants: Japan Display Inc. - Inventors: Akihiro Hanada; Takuo Kaitoh; Masashi Tsubuku - Web page: https://patentgrep.com/patent/US12191398B2 ## CPC - H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate} - H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes} - H10D 30/6733: {Multi-gate TFTs} - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract The purpose of the present invention is to suppress a variation in a threshold voltage (Δ Vth) in a Thin Film Transistor (TFT) using an oxide semiconductor. The present invention takes a structure as follows to attain this purpose. A semiconductor device having TFT using an oxide semiconductor including: a channel region, a source region, a drain region, and a transition region between the channel region and the source region and between the channel region and the drain region, in which a resistivity of the transition region is smaller than that of the channel region, and larger than that of the source region or the drain region; a source electrode is formed overlapping the source region, and a drain electrode is formed overlapping the drain region; and a thickness of the transition region of the oxide semiconductor is larger than a thickness of the channel region of the oxide semiconductor. ## Claims ### Claim 1 A semiconductor device having TFT using an oxide semiconductor comprising: the oxide semiconductor including a channel region, a source region, a drain region, and a transition region between the channel region and the source region and between the channel region and the drain region, wherein a resistivity of the transition region is smaller than that of the channel region, and larger than that of the source region or the drain region, a source electrode is formed overlapping the source region, and a drain electrode is formed overlapping the drain region, a thickness of the transition region of the oxide semiconductor is larger than a thickness of the channel region of the oxide semiconductor, a first gate insulating film covers the oxide semiconductor, a second gate insulating film covers the first gate insulating film, a through hole is formed in the second gate insulating film at a place corresponding to the transition region of the oxide semiconductor, and a gate electrode is formed covering the second gate insulating film and the through hole. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein, in the oxide semiconductor, a thickness of the source region or a thickness of the drain region is larger than a thickness of the transition region. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein, in the oxide semiconductor, a thickness of the channel region is 60 nm or less when measured at a center of the channel region, and a thickness of the transition region measured at a center of the transition region is 85 nm or more. ### Claim 4 (depends on 2) The semiconductor device according to claim 2, wherein, in the oxide semiconductor, a thickness of the channel region is 60 nm or less when measured at a center of the channel region, and a thickness of the transition region measured at a center of the transition region is 85 nm or more. ### Claim 5 (depends on 2) The semiconductor device according to claim 2, wherein a difference in thickness between the source region and the transition region or a difference in thickness between the drain region and the transition region is 10 nm or more. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein a length of the transition region in a direction of a channel length is 2 microns or more. ### Claim 7 (depends on 2) The semiconductor device according to claim 2, wherein a length of the transition region in a direction of channel length is 2 microns or more. ### Claim 8 (depends on 3) The semiconductor device according to claim 3, wherein a length of the transition region in a direction of channel length is 2 microns or more. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, wherein the TFT is a bottom gate type TFT. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, wherein the TFT is a dual gate type TFT which has a bottom gate and a top gate. ### Claim 11 (depends on 1) The semiconductor device according to claim 1, wherein ions are doped in the transition region to raise a conductivity of the oxide semiconductor. ### Claim 12 A semiconductor device having TFT using an oxide semiconductor comprising: the oxide semiconductor including a channel region, a source region, a drain region, and a transition region between the channel region and the source region and between the channel region and the drain region, wherein a resistivity of the transition region is smaller than that of the channel region, and larger than that of the source region or the drain region, a source electrode is formed overlapping the source region, and a drain electrode is formed overlapping the drain region, a first gate insulating film is formed covering the oxide semiconductor, a second gate insulating film is formed covering the first gate insulating film, a through hole is formed in the second gate insulating film at a place corresponding the transition region of the oxide semiconductor, and a gate electrode is formed covering the second insulating film and the through hole. ### Claim 13 (depends on 12) The semiconductor device according to claim 12, wherein a thickness of the transition region is 60 nm or less. ### Claim 14 (depends on 12) The semiconductor device according to claim 12, wherein a length of the transition region in a direction of a channel length is 2 microns or more. ### Claim 15 (depends on 12) The semiconductor device according to claim 12, wherein a third gate insulating film is formed under the oxide semiconductor, and a second gate electrode is formed under the third gate insulating film.