# US 12,191,395 B2 · Dual gate control for trench shaped thin film transistors

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- Number: US 12,191,395 B2
- Document ID: US12191395B2
- Status: Granted
- Kind: B2
- Application number: 18/494,384
- Filed: 2023-10-25
- Published: 2024-02-15
- Granted: 2025-01-07
- Earliest claimed: 2018-03-28
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Abhishek A. Sharma; Van H. Le; Gilbert Dewey; Jack T. Kavalieros; Shriram Shivaraman; Benjamin Chu-Kung; Yih Wang; Tahir Ghani
- Web page: https://patentgrep.com/patent/US12191395B2

## CPC

- H10D 30/6728: {Vertical TFTs}
- H10B 12/05: {Making the transistor}
- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- H10B 12/315: {with the capacitor higher than a bit line}
- H10B 12/50: {Peripheral circuit region structures}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 30/674: {characterised by the active materials}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 62/40: Crystalline structures
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10P 14/276: {Lateral overgrowth}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10P 50/283: {by chemical means}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.

## Claims

### Claim 1

A method of fabricating a thin film transistor structure, comprising:
forming a trench extending through a source and drain material layer, a first semiconductor layer, and a dielectric layer to expose a surface of a first gate dielectric layer, wherein the first gate dielectric layer is over a first gate electrode;
growing a second semiconductor layer from the first semiconductor layer and over the dielectric layer and the surface of the first gate dielectric layer to form a non-planar semiconductor layer having a portion over the surface of the first gate dielectric layer;
disposing a second gate dielectric layer over the portion of the non-planar semiconductor layer; and
disposing a second gate electrode at least partially within the trench, wherein the second gate dielectric layer is between the portion of the non-planar semiconductor layer and the second gate electrode.

### Claim 2 (depends on 1)

The method of claim 1, wherein the second gate dielectric layer comprises a portion that extends along a sidewall of the second gate electrode within the trench.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
disposing a dielectric spacer on a sidewall portion of the non-planar semiconductor layer, wherein disposing the second gate dielectric layer comprises disposing the second gate dielectric layer on at least a sidewall of the dielectric spacer.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
disposing a second source and drain material layer on a sidewall portion of the non-planar semiconductor layer and the portion of the non-planar semiconductor layer; and
removing at least a portion of the second source and drain material layer to expose the portion of the non-planar semiconductor layer, wherein disposing the second gate dielectric layer comprises disposing the second gate dielectric layer on at least a sidewall of the second source and drain material layer.

### Claim 5 (depends on 1)

The method of claim 1, wherein growing the second semiconductor layer from the first semiconductor layer comprises growing a portion of the second semiconductor layer over at least a portion of an exposed surface of the source and drain material layer, the method further comprising:
providing a bulk material over the first and second semiconductor layers;
performing a recess etch to remove the portion of the second semiconductor layer over the exposed surface of the source and drain material layer; and
removing remaining portions of the bulk material.

### Claim 6 (depends on 1)

The method of claim 1, wherein the non-planar semiconductor layer comprises an amorphous or polycrystalline semiconductor material.

### Claim 7 (depends on 1)

The method of claim 1, wherein the first and second gate electrodes comprise different materials.

### Claim 8

A method of fabricating a thin film transistor structure, comprising:
forming a trench extending through a metal layer, a first semiconductor layer, and a dielectric layer to expose a surface of a first gate dielectric layer, wherein the first gate dielectric layer is over a first gate electrode;
growing a second semiconductor layer from the first semiconductor layer and over the dielectric layer and the surface of the first gate dielectric layer to form a non-planar semiconductor layer having a portion over the surface of the first gate dielectric layer;
disposing a second gate dielectric layer over the portion of the non-planar semiconductor layer; and
disposing a second gate electrode at least partially within the trench, wherein the second gate dielectric layer is between the portion of the non-planar semiconductor layer and the second gate electrode.

### Claim 9 (depends on 8)

The method of claim 8, wherein the second gate dielectric layer comprises a portion that extends along a sidewall of the second gate electrode within the trench.

### Claim 10 (depends on 8)

The method of claim 8, further comprising:
disposing a dielectric spacer on a sidewall portion of the non-planar semiconductor layer, wherein disposing the second gate dielectric layer comprises disposing the second gate dielectric layer on at least a sidewall of the dielectric spacer.

### Claim 11 (depends on 8)

The method of claim 8, further comprising:
disposing a second metal layer on a sidewall portion of the non-planar semiconductor layer and the portion of the non-planar semiconductor layer; and
removing at least a portion of the second metal layer to expose the portion of the non-planar semiconductor layer, wherein disposing the second gate dielectric layer comprises disposing the second gate dielectric layer on at least a sidewall of the second metal layer.

### Claim 12 (depends on 8)

The method of claim 8, wherein growing the second semiconductor layer from the first semiconductor layer comprises growing a portion of the second semiconductor layer over at least a portion of an exposed surface of the metal layer, the method further comprising:
providing a bulk material over the first and second semiconductor layers;
performing a recess etch to remove the portion of the second semiconductor layer over the exposed surface of the metal layer; and
removing remaining portions of the bulk material.

### Claim 13 (depends on 8)

The method of claim 8, wherein the non-planar semiconductor layer comprises an amorphous or polycrystalline semiconductor material.

### Claim 14 (depends on 8)

The method of claim 8, wherein the first and second gate electrodes comprise different materials.

### Claim 15

A method of fabricating a thin film transistor structure comprising:
forming a trench extending through a source and drain material layer, a first thin film semiconductor layer, and a dielectric layer to expose a surface of a first gate dielectric layer, wherein the first gate dielectric layer is over a first gate electrode structure;
growing a second thin film semiconductor layer from the first thin film semiconductor layer and over the dielectric layer and the surface of the first gate dielectric layer to form a non-planar thin film semiconductor layer having a portion over the surface of the first gate dielectric layer;
disposing a second gate dielectric layer over the portion of the non-planar thin film semiconductor layer; and
disposing a second gate electrode structure at least partially within the trench, wherein the second gate dielectric layer is between the portion of the non-planar thin film semiconductor layer and the second gate electrode structure.

### Claim 16 (depends on 15)

The method of claim 15, wherein the second gate dielectric layer comprises a portion that extends along a sidewall of the second gate electrode structure within the trench.

### Claim 17 (depends on 15)

The method of claim 15, further comprising:
disposing a dielectric spacer layer on a sidewall portion of the non-planar thin film semiconductor layer, wherein disposing the second gate dielectric layer comprises disposing the second gate dielectric layer on at least a sidewall of the dielectric spacer layer.

### Claim 18 (depends on 15)

The method of claim 15, further comprising:
disposing a second source and drain material layer on a sidewall portion of the non-planar thin film semiconductor layer and the portion of the non-planar thin film semiconductor layer; and
removing at least a portion of the second source and drain material layer to expose the portion of the non-planar thin film semiconductor layer, wherein disposing the second gate dielectric layer comprises disposing the second gate dielectric layer on at least a sidewall of the second source and drain material layer.

### Claim 19 (depends on 15)

The method of claim 15, wherein growing the second thin film semiconductor layer from the first thin film semiconductor layer comprises growing a portion of the second thin film semiconductor layer over at least a portion of an exposed surface of the source and drain material layer, the method further comprising:
providing a bulk material over the first and second thin film semiconductor layers;
performing a recess etch to remove the portion of the second thin film semiconductor layer over the exposed surface of the source and drain material layer; and
removing remaining portions of the bulk material.

### Claim 20 (depends on 15)

The method of claim 15, wherein the non-planar thin film semiconductor layer comprises an amorphous or polycrystalline semiconductor material.