# US 12,191,394 B2 · Strained vertical channel semiconductor device, method of manufacturing the same, and electronic apparatus including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,191,394 B2 - Document ID: US12191394B2 - Status: Granted - Kind: B2 - Application number: 17/643,179 - Filed: 2021-12-07 - Published: 2022-06-16 - Granted: 2025-01-07 - Earliest claimed: 2020-12-11 - Assignees: Institute of Microelectronics, Chinese Academy of Sciences - Applicants: Institute of Microelectronics, Chinese Academy of Sciences - Inventors: Huilong Zhu - Web page: https://patentgrep.com/patent/US12191394B2 ## CPC - H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) - H10D 30/6728: {Vertical TFTs} - H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)} - H10D 30/031: {of thin-film transistors [TFT]} - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 30/791: {Arrangements for exerting mechanical stress on the crystal lattice of the channel regions} - H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain} - H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)} - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10P 32/141: {the applied layer comprising oxides only} - H10P 32/171: {being group IV material} - H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions - H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A strained vertical channel semiconductor device, a method of manufacturing the same, and an electronic apparatus including the same are provided. The method includes: providing a vertical channel layer on a substrate, wherein the vertical channel layer is held by a first supporting layer on a first side in a lateral direction, and is held by a second supporting layer on a second side opposite to the first side; replacing the first supporting layer with a first gate stack while the vertical channel layer is held by the second supporting layer; and replacing the second supporting layer with a second gate stack while the vertical channel layer is held by the first gate stack. ## Claims ### Claim 1 A semiconductor device, comprising: a vertical channel portion on a substrate; source and drain portions located at an upper end of the channel portion and a lower end of the channel portion relative to the substrate; and a first gate stack on a first side of the channel portion in a lateral direction, and a second gate stack on a second side of the channel portion in the lateral direction, wherein the second side is opposite to the first side, wherein a first gate dielectric layer in the first gate stack partially overlaps with a second gate dielectric layer in the second gate stack so as to form a stack of the first gate dielectric layer and the second gate dielectric layer, and a thickness of at least part of the stack is a sum of a thickness of the first gate dielectric layer and a thickness of the second gate dielectric layer. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the channel portion comprises a curved nanosheet or nanowire with a C-shaped section. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein a part of each of the first gate stack and the second gate stack at least close to the channel portion is substantially coplanar with the channel portion. ### Claim 4 (depends on 2) The semiconductor device according to claim 2, wherein the curved nanosheet or nanowire has a substantially uniform thickness. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein an overlapping portion of the first gate dielectric layer and the second gate dielectric layer is different from parts of the first gate dielectric layer and the second gate dielectric layer facing the channel portion. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein the channel portion has a stress in a vertical direction. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein a lattice constant of a material of the channel portion is different from a lattice constant of said material without being strained. ### Claim 8 (depends on 6) The semiconductor device according to claim 6, wherein the semiconductor device is a n-type MOSFET, the channel portion has a tensile stress or a tensile strain in the vertical direction, or in the vertical direction, a lattice constant of a material of the channel portion is greater than a lattice constant of said material without being strained; or the semiconductor device is a p-type MOSFET, the channel portion has a compressive stress or a compressive strain in the vertical direction, or in the vertical direction, a lattice constant of a material of the channel portion is less than a lattice constant of said material without being strained. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, further comprising another semiconductor layer arranged side by side with the channel portion. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, wherein: the channel portion comprises a first surface and a second surface opposite to each other, and a third surface and a fourth surface opposite to each other, the first gate dielectric layer extends along the first surface, the third surface and the fourth surface, and the second gate dielectric layer extends along the second surface and along a part of the first gate dielectric layer extending along the third surface and the fourth surface. ### Claim 11 (depends on 1) An electronic apparatus, comprising the semiconductor device according to claim 1. ### Claim 12 (depends on 11) The electronic apparatus according to claim 11, wherein the electronic apparatus comprises a smart phone, a personal computer, a tablet computer, a wearable smart apparatus, an artificial intelligence apparatus, or a mobile power supply.