# US 12,191,393 B2 · Low Ge isolated epitaxial layer growth over nano-sheet architecture design for RP reduction

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- Number: US 12,191,393 B2
- Document ID: US12191393B2
- Status: Granted
- Kind: B2
- Application number: 17/239,328
- Filed: 2021-04-23
- Published: 2022-10-27
- Granted: 2025-01-07
- Earliest claimed: 2021-04-23
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yan-Ting Lin; Yen-Ru Lee; Chien-Chang Su; Chih-Yun Chin; Chien-Wei Lee; Pang-Yen Tsai; Chii-Horng Li; Yee-Chia Yeo
- Web page: https://patentgrep.com/patent/US12191393B2

## CPC

- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/271: {characterised by the preparation of substrate for selective deposition}
- H10P 14/3408: {Silicon carbide}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3442: {N-type}
- H10P 14/3452: {Microstructure}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A nano-FET and a method of forming is provided. In some embodiments, a nano-FET includes an epitaxial source/drain region contacting ends of a first nanostructure and a second nanostructure. The epitaxial source/drain region may include a first semiconductor material layer of a first semiconductor material, such that the first semiconductor material layer includes a first segment contacting the first nanostructure and a second segment contacting the second nanostructure, wherein the first segment is separated from the second segment. A second semiconductor material layer is formed over the first segment and the second segment. The second semiconductor material layer may include a second semiconductor material having a higher concentration of dopants of a first conductivity type than the first semiconductor material layer. The second semiconductor material layer may have a lower concentration percentage of silicon than the first semiconductor material layer.

## Claims

### Claim 1

A nano-FET comprising:
a substrate, the substrate comprising a fin;
isolation regions over the substrate and along opposing sides of the fin;
a plurality of first nanostructures over the fin;
an epitaxial source/drain region adjacent the plurality of first nanostructures, the epitaxial source/drain region comprises:
a first semiconductor material layer comprising first semiconductor material segments and a second semiconductor material segment, each of the first semiconductor material segments contacting an end of at least one of the plurality of first nanostructures, each of the first semiconductor material segments being separated from others of the first semiconductor material segments, the first semiconductor material segments having a first dopant concentration of dopants of a first conductivity type; and
a second semiconductor material layer having a second dopant concentration of dopants of the first conductivity type, the second dopant concentration being greater than the first dopant concentration, the second semiconductor material layer comprising a single layer covering each of the first semiconductor material segments; and
a gate electrode over the plurality of first nanostructures;
wherein each of the first semiconductor material segments have a first thickness, each of the plurality of first nanostructures have a second thickness, the first thickness is greater than the second thickness for each first semiconductor material segment in contact with the end of the at least one of the plurality of first nanostructures, each nanostructure of the plurality of first nanostructures being separated by the gate electrode, a spacer is disposed between the gate electrode and the epitaxial source/drain region, the spacer being further disposed between adjacent nanostructures of the plurality of first nanostructures, and an interface between each nanostructure of the plurality of first nanostructures and each of the first semiconductor material segments having a shape curving outwards towards the epitaxial source drain region at the center; and
wherein the second semiconductor material segment is on a recessed portion of the substrate adjacent to the fin, the second semiconductor material segment is discontinuous from the first semiconductor material segments, the second semiconductor material segment has the first dopant concentration of the first conductivity type.

### Claim 2 (depends on 1)

The nano-FET of claim 1, wherein the first dopant concentration is between 1×1020 atoms/cm3 and 5×1020 atoms/cm3.

### Claim 3 (depends on 2)

The nano-FET of claim 2, wherein the second dopant concentration is between 5×1020 atoms/cm3 and 10×1020 atoms/cm3.

### Claim 4 (depends on 1)

The nano-FET of claim 1, wherein the first semiconductor material segments comprise Si1-x_L1Gex_L1, wherein x_L1 is between 0.1 and 0.4.

### Claim 5 (depends on 4)

The nano-FET of claim 4, wherein the second semiconductor material layer comprises Si1-x_L2Gex_L2, wherein x_L2 is greater than or equal to 0.2 and less than or equal to 0.9, wherein x_L2 is greater than x_L1.

### Claim 6 (depends on 1)

The nano-FET of claim 1, wherein the epitaxial source/drain region further comprises a third semiconductor material layer formed over the second semiconductor material layer, the third semiconductor material layer comprising a different material than the second semiconductor material layer.

### Claim 7 (depends on 1)

The nano-FET of claim 1, wherein each of the first semiconductor material segments contacts a single nanostructure of the plurality of first nanostructures.

### Claim 8

A nano-FET comprising:
a substrate;
a first nanostructure and a second nanostructure over the substrate in a stack;
an epitaxial source/drain region contacting ends of the first nanostructure and the second nanostructure, the epitaxial source/drain region comprising:
a first semiconductor material layer comprising a first semiconductor material, the first semiconductor material layer comprising a first segment contacting the first nanostructure, a second segment contacting the second nanostructure, and a third segment contacting a recessed portion of the substrate, wherein the first segment, the second segment, and the third segment are each discontinuous from each other; and
a second semiconductor material layer over the first segment, the second segment, and the third segment, the second semiconductor material layer comprising a second semiconductor material, wherein the second semiconductor material layer has a higher concentration of dopants of a first conductivity type than the first semiconductor material layer, wherein the second semiconductor material layer and the first semiconductor material layer are silicon-based materials, wherein the second semiconductor material layer has a lower concentration percentage of silicon than the first semiconductor material layer; and
a gate electrode between the first nanostructure and the second nanostructure, wherein a spacer separates the gate electrode from the epitaxial source/drain region, the spacer being further disposed between the first nanostructure and the second nanostructure;
wherein interfaces between the first nanostructure and the first segment, and the second nanostructure and the first segment, have a shape curving inwards away from the epitaxial source drain region at the center.

### Claim 9 (depends on 8)

The nano-FET of claim 8, further comprising a third nanostructure in the stack over the second nanostructure, wherein the second segment extends continuously from the second nanostructure to the third nanostructure, wherein the gate electrode extends over the third nanostructure.

### Claim 10 (depends on 8)

The nano-FET of claim 8, wherein the first semiconductor material comprises Si1-x_L1Gex_L1, X_L1 being is between 0.1 and 0.4, wherein the second semiconductor material comprises Si1-x_L2Gex_L2, x_L2 being greater than or equal to 0.2 and less than or equal to 0.9, x_L2 being greater than x_L1.

### Claim 11 (depends on 8)

The nano-FET of claim 8, wherein the first semiconductor material has a first dopant concentration of boron between 1×1020 atoms/cm3 and 5×1020 atoms/cm3, wherein
the second semiconductor material has a second dopant concentration of boron between 5×1020 atoms/cm3 and 10×1020 atoms/cm3.

### Claim 12 (depends on 11)

The nano-FET of claim 11, wherein the first semiconductor material layer has a thickness between 2 nanometers and 6 nanometers.

### Claim 13

A method for forming a nano-FET, the method comprising:
forming a plurality of nanostructure layers comprising alternating layers of a first semiconductor material and a second semiconductor material;
forming a first recess in the plurality of nanostructure layers to form a stack of a plurality of first nanostructures, ends of the plurality of first nanostructures being exposed in the first recess;
recessing ends of the plurality of first nanostructures of the second semiconductor material to form a second recess;
forming inner spacers in the second recess on the ends of the plurality of first nanostructures of the second semiconductor material;
forming source/drain regions in the first recess, wherein forming the source/drain regions comprising:
epitaxially growing a first semiconductor material layer on each end of the plurality of first nanostructures of the first semiconductor material and on an exposed and recessed portion of a semiconductor substrate adjacent to the plurality of first nanostructures, wherein the first semiconductor material layer is discontinuous between growth on a first plurality of end of the plurality of first nanostructures and the exposed portion of the semiconductor substrate, wherein the first semiconductor material layer is merged across a second plurality of ends of the first plurality of first nanostructures; and
epitaxially growing a second semiconductor material layer over each of the first semiconductor material layers, wherein the first semiconductor material layer has a lower concentration of dopants of a first conductivity type than the second semiconductor material layer.

### Claim 14 (depends on 13)

The method of claim 13, wherein a dopant concentration of dopants of the first conductivity type in the first semiconductor material layer is between 1×1020 atoms/cm3 and 5×1020 atoms/cm3, wherein a dopant concentration of dopants of the first conductivity type in the second semiconductor material layer is between 5×1020 atoms/cm3 and 10×1020 atoms/cm3.

### Claim 15 (depends on 13)

The method of claim 13, wherein the first semiconductor material layer and the second semiconductor material layer comprise silicon germanium, wherein the second semiconductor material layer has a higher concentration of germanium than the first semiconductor material layer, and wherein the first semiconductor material layer on each end of the plurality of first nanostructures of the first semiconductor material is thicker than a nanostructure of the plurality of first nanostructures from which the first semiconductor material layer is epitaxially grown.

### Claim 16 (depends on 15)

The method of claim 15, wherein the first semiconductor material layer comprises Si1-x_L1Gex_L1, wherein x_L1 is between 0.1 and 0.4.

### Claim 17 (depends on 16)

The method of claim 16, wherein the second semiconductor material layer comprises Si1-x_L2Gex_L2, wherein x_L2 is greater than or equal to 0.2 and less than or equal to 0.9, wherein X_L2 is greater than x_L1.

### Claim 18 (depends on 13)

The method of claim 13, wherein the source/drain region comprises a third semiconductor material layer formed over the second semiconductor material layer.

### Claim 19 (depends on 13)

The method of claim 13, wherein the first semiconductor material layer is discontinuous across each inner spacer between adjacent nanostructures.

### Claim 20 (depends on 13)

The method of claim 13, wherein the first semiconductor material layer is grown to a thickness between 2 nanometers and 6 nanometers.