# US 12,191,390 B2 · Semiconductor device including stacked semiconductor patterns

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- Number: US 12,191,390 B2
- Document ID: US12191390B2
- Status: Granted
- Kind: B2
- Application number: 18/518,004
- Filed: 2023-11-22
- Published: 2024-03-14
- Granted: 2025-01-07
- Earliest claimed: 2020-12-07
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Junggun You; Yoonjoong Kim; Seungwoo Do; Sungil Park
- Web page: https://patentgrep.com/patent/US12191390B2

## CPC

- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 30/506: {having different thicknesses, sizes or shapes}
- H10D 30/751: {having composition variations in the channel regions}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device including a substrate that includes first to third regions; a first channel structure on the first region and including first channel patterns that are vertically stacked on the substrate; a second channel structure on the second region and including a second channel pattern on the substrate; a third channel structure on the third region and including third channel patterns and fourth channel patterns that are vertically and alternately stacked on the substrate; first to third gate electrodes on the first to third channel structures; and first to third source/drain patterns on opposite sides of the first to third channel structures, wherein the first, second, and fourth channel patterns include a first semiconductor material, and the third channel patterns include a second semiconductor material different from the first semiconductor material.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate that includes a first region, a second region, and a third region;
a plurality of first semiconductor patterns that are vertically stacked on the first region;
a second semiconductor pattern on the second region;
a plurality of third semiconductor patterns and a plurality of fourth semiconductor patterns that are vertically and alternately stacked on the third region;
a first electrode on the plurality of first semiconductor patterns, a second electrode on the second semiconductor pattern, and a third electrode on the plurality of third semiconductor patterns; and
a first source/drain pattern on opposite sides of the plurality of first semiconductor patterns,
wherein:
the plurality of first semiconductor patterns, the second semiconductor pattern, and the plurality of fourth semiconductor patterns each include a first semiconductor material, and
the plurality of third semiconductor patterns include a second semiconductor material different from the first semiconductor material.

### Claim 2 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the first electrode has a first line-width, the second electrode has a second line-width and the third electrode has a third line-width, and
the first line-width is different from the second line-width and the third line-width.

### Claim 3 (depends on 2)

The semiconductor device as claimed in claim 2, wherein the first line-width is less than the second line-width and the third line-width.

### Claim 4 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the first electrode extends across the plurality of first semiconductor patterns and surrounds each first semiconductor pattern of the plurality of first semiconductor patterns.

### Claim 5 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising a first dielectric layer between the first electrode and the plurality of first semiconductor patterns, a second dielectric layer between the second electrode and the second semiconductor pattern, and a third dielectric layer between the third electrode and the plurality of third semiconductor pattern,
wherein the first dielectric layer conformally covers a surface of each first semiconductor pattern of the plurality of first semiconductor patterns.

### Claim 6 (depends on 1)

The semiconductor device as claimed in claim 1, wherein
the second electrode extends across the second semiconductor pattern and covers opposite sidewalls of the second semiconductor pattern, and
the third electrode covers opposite sidewalls of the plurality of third semiconductor patterns and opposite sidewalls of the plurality of fourth semiconductor patterns.

### Claim 7 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the first semiconductor material and the second semiconductor material each independently include silicon, germanium, silicon-germanium, or a III-V group compound semiconductor.

### Claim 8 (depends on 1)

The semiconductor device as claimed in claim 1, wherein:
the first semiconductor material includes silicon, and
the second semiconductor material includes silicon-germanium.

### Claim 9

A semiconductor device, comprising:
a substrate that includes a first region, a second region, and a third region;
a first structure on the first region, the first structure including a plurality of first semiconductor patterns that are vertically stacked on the substrate;
a second structure on the second region, the second structure including a second semiconductor pattern on the substrate;
a third structure on the third region, the third structure including a plurality of third semiconductor patterns and a plurality of fourth semiconductor patterns that are vertically and alternately stacked on the substrate;
a first electrode on the first structure, a second electrode on the second structure, and a third electrode on the third structure;
a first dielectric layer between the first electrode and the first structure, a second dielectric layer between the second electrode and the second structure, and a third dielectric layer between the third electrode and the third structure; and
first source/drain patterns on opposite sides of the first structure and second source/drain patterns on opposite sides of the second structure,
wherein:
the third structure has an uneven sidewall, and
the third dielectric layer covers the uneven sidewall.

### Claim 10 (depends on 9)

The semiconductor device as claimed in claim 9, wherein sidewalls of the plurality of third semiconductor patterns are laterally recessed to a greater depth than a depth to which sidewalls of the plurality of fourth semiconductor patterns are laterally recessed.

### Claim 11 (depends on 9)

The semiconductor device as claimed in claim 9, wherein each third semiconductor pattern of the plurality of third semiconductor patterns has a rounded sidewall.

### Claim 12 (depends on 9)

The semiconductor device as claimed in claim 9, wherein the first electrode has a first line-width, the second electrode has a second line-width and the third electrode has a third line-width, and
the first line-width is different from the second line-width and the third line-width.

### Claim 13 (depends on 12)

The semiconductor device as claimed in claim 12, wherein the first line-width is less than the second line-width and the third line-width.

### Claim 14 (depends on 9)

The semiconductor device as claimed in claim 9, wherein a first distance between the first source/drain patterns is less than a second distance between the second source/drain patterns.

### Claim 15

A semiconductor device, comprising:
a substrate that includes a first region, a second region, and a third region;
a first structure on the first region, the first structure including a plurality of first semiconductor patterns that are vertically stacked on the substrate;
a second structure on the second region, the second structure including a second semiconductor pattern on the substrate;
a third structure on the third region, the third structure having an uneven sidewall and including a plurality of third semiconductor patterns and a plurality of fourth semiconductor patterns that are vertically and alternately stacked on the substrate;
a first electrode on the first structure, a second electrode on the second structure, and a third electrode on the third structure;
a first dielectric layer between the first electrode and the first structure, a second dielectric layer between the second electrode and the second structure, and a third dielectric layer between the third electrode and the third structure; and
a first source/drain pattern on opposite sides of the first structure, a second source/drain pattern on opposite sides of the second structure, and a third source/drain pattern on opposite sides of the third structure,
wherein:
the plurality of first semiconductor patterns, the second semiconductor pattern, and the plurality of fourth semiconductor patterns each include silicon, and
the plurality of third semiconductor patterns each include silicon-germanium.

### Claim 16 (depends on 15)

The semiconductor device as claimed in claim 15, wherein sidewalls of the plurality of third semiconductor patterns are laterally recessed to a greater depth than a depth to which sidewalls of the plurality of fourth semiconductor patterns are laterally recessed.

### Claim 17 (depends on 15)

The semiconductor device as claimed in claim 15, wherein each third semiconductor pattern of the plurality of third semiconductor patterns has a rounded sidewall.

### Claim 18 (depends on 15)

The semiconductor device as claimed in claim 15, wherein the first electrode extends across the first structure and surrounds each first semiconductor pattern of the plurality of first semiconductor patterns.

### Claim 19 (depends on 18)

The semiconductor device as claimed in claim 18, wherein the first dielectric layer conformally covers a surface of each first semiconductor pattern of the plurality of first semiconductor patterns.

### Claim 20 (depends on 15)

The semiconductor device as claimed in claim 15, wherein:
the second electrode extends across the second structure and covers opposite sidewalls of the second semiconductor pattern, and
the third electrode extends across the third structure and covers opposite sidewalls of the plurality of third semiconductor patterns and sidewalls of the plurality of fourth semiconductor patterns.