# US 12,191,389 B2 · Layered structure, semiconductor device including the same, and manufacturing method thereof

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,191,389 B2
- Document ID: US12191389B2
- Status: Granted
- Kind: B2
- Application number: 16/953,278
- Filed: 2020-11-19
- Published: 2021-12-16
- Granted: 2025-01-07
- Earliest claimed: 2020-06-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Mauricio Manfrini; Han-Jong Chia
- Web page: https://patentgrep.com/patent/US12191389B2

## CPC

- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/033: {comprising ferroelectric layers}
- H10D 64/689: {having ferroelectric layers}
- H10B 51/30: characterised by the memory core region
- H10B 53/30: characterised by the memory core region
- H10D 1/682: {having dielectrics comprising perovskite structures}
- H10D 30/0415: {of FETs having ferroelectric gate insulators}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor device includes a transistor and a ferroelectric tunnel junction. The ferroelectric tunnel junction is connected to a drain contact of the transistor. The ferroelectric tunnel junction includes a first electrode, a second electrode, a crystalline oxide layer, and a ferroelectric layer. The second electrode is disposed over the first electrode. The crystalline oxide layer and the ferroelectric layer are disposed in direct contact with each other in between the first electrode and the second electrode. The crystalline oxide layer comprises a crystalline oxide material. The ferroelectric layer comprises a ferroelectric material.

## Claims

### Claim 1

A semiconductor device, comprising:
a field-effect transistor, comprising:
a gate structure disposed on a semiconductor channel of a semiconductor substrate;
a source region and a drain region disposed in the semiconductor substrate at opposite ends of the semiconductor channel;
an interlayer dielectric layer disposed on the semiconductor substrate and surrounding the gate structure; and
a source contact and a drain contact extending through the interlayer dielectric layer to contact the source region and the drain region, wherein top surfaces of the source contact and the drain contact are flushed with a top surface of the gate structure;
a thin film transistor, disposed over and electrically to the field-effect transistor, and comprising:
a semiconductor oxide channel pattern;
a gate pattern disposed over the semiconductor oxide channel pattern;
two metal contacts disposed over the semiconductor oxide channel pattern and beside the gate pattern; and
a high-k dielectric pattern disposed between the gate pattern and the semiconductor oxide channel pattern and in contact with the two metal contacts, wherein the high-k dielectric pattern is disposed only between facing inner sidewalls of the metal contacts, a width of the high-k dielectric pattern is less than a width of the semiconductor oxide channel pattern, and sidewalls of the semiconductor oxide channel pattern are respectively flushed with outer sidewalls of the metal contacts; and
a ferroelectric tunnel junction disposed over and electrically connected to one of the metal contacts of the thin film transistor, wherein the ferroelectric tunnel junction comprises:
a first electrode;
a second electrode, disposed over the first electrode; and
a layered structure comprising at least two crystalline oxide layers and at least two ferroelectric layers disposed alternately and in direct contact with each other between the first electrode and the second electrode, wherein each of the first electrode and the second electrode is TiN, TaN, or a combination thereof, and a bottommost crystalline oxide layer of the layered structure is in direct contact with the first electrode, and wherein a topmost ferroelectric layer of the layered structure is in direct contact with the second electrode.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a top surface of the semiconductor oxide channel pattern is in contact with the high-k dielectric pattern, and a sidewall of the semiconductor oxide channel pattern is in contact with a dielectric material different from the high-k dielectric pattern.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the field-effect transistor further comprising spacers on sidewalls of the gate structure, and top surfaces of the spacers are flushed with then the top surfaces of the source contact and the drain contact.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the adjacent crystalline oxide layer and the ferroelectric layer are in direct contact with each other.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the crystalline oxide layers include the same crystalline oxide material.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the ferroelectric tunnel junction has an inclined sidewall.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the topmost layer is in contact with the second electrode.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the at least one of the crystalline oxide layers has a crystal lattice orientation (110).

### Claim 9

A semiconductor device, comprising:
a field-effect transistor, comprising:
a gate structure disposed on a semiconductor channel of a semiconductor substrate;
a source region and a drain region disposed in the semiconductor substrate at opposite ends of the semiconductor channel;
an interlayer dielectric layer disposed on the semiconductor substrate and surrounding the gate structure; and
a source contact and a drain contact extending through the interlayer dielectric layer to contact the source region and the drain region, wherein top surfaces of the source contact and the drain contact are flushed with a top surface of the gate structure;
a thin film transistor disposed over and electrically to the field-effect transistor, and comprising a channel pattern comprising a semiconductor oxide; and
a ferroelectric tunnel junction, disposed over and electrically connected to the thin film transistor, wherein the ferroelectric tunnel junction comprises:
a bottom electrode and a top electrode; and
a layered structure, disposed between the bottom electrode and the top electrode and comprising at least two crystalline oxide layers and at least two ferroelectric layers stacked alternately and in direct contact with each other, wherein each ferroelectric layer is hafnium oxide, hafnium zirconium oxide, hafnium lanthanum oxide, hafnium aluminum oxide, or hafnium silicon oxide, and a topmost layer and a bottommost layer are both crystalline oxide layers, wherein each of the bottom electrode and the top electrode is TiN, TaN, or a combination thereof, and the bottommost crystalline oxide layer of the layered structure is in direct contact with the bottom electrode, and wherein a topmost ferroelectric layer of the layered structure is in direct contact with the top electrode.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the topmost layer of the layered structure in contact with the top electrode.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein the crystalline oxide layers include the same crystalline oxide material.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, wherein the ferroelectric layers have orthorhombic phase.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, wherein the ferroelectric tunnel junction has an inclined sidewall.

### Claim 14 (depends on 9)

The semiconductor device of claim 9, wherein the at least one crystalline oxide layer has a crystal lattice orientation (110).

### Claim 15

A semiconductor device, comprising:
a field-effect transistor, comprising:
a gate structure disposed on a semiconductor channel of a semiconductor substrate;
a source region and a drain region disposed in the semiconductor substrate at opposite ends of the semiconductor channel;
an interlayer dielectric layer disposed on the semiconductor substrate and surrounding the gate structure; and
a source contact and a drain contact extending through the interlayer dielectric layer to contact the source region and the drain region, wherein top surfaces of the source contact and the drain contact are flushed with a top surface of the gate structure;
a thin film transistor disposed over and electrically to the field-effect transistor, and comprising:
a channel pattern comprising a semiconductor oxide;
a gate pattern disposed over the channel pattern; and
two contacts disposed over the channel pattern and beside the gate pattern, wherein top surfaces of the two contacts are flushed with a top surface of the gate pattern, the high-k dielectric pattern is disposed only between facing inner sidewalls of the contacts, and a width of the high-k dielectric pattern is less than a width of the channel pattern, and sidewalls of the channel pattern are respectively flushed with outer sidewalls of the contacts; and
a ferroelectric tunnel junction electrically connected to one of the contacts of the second transistor, wherein the ferroelectric tunnel junction comprises:
a first electrode;
a second electrode, disposed over the first electrode; and
a layered structure comprising at least two crystalline oxide layers and at least two ferroelectric layers disposed alternately and in direct contact with each other between the first electrode and the second electrode, wherein each of the first electrode and the second electrode is TiN, TaN, or a combination thereof, and the bottommost crystalline oxide layer of the layered structure is in direct contact with the first electrode, and wherein a topmost ferroelectric layer of the layered structure is in direct contact with the second electrode.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the ferroelectric tunnel junction has an inclined sidewall.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein the crystalline oxide layers include the same crystalline oxide material.

### Claim 18 (depends on 15)

The semiconductor device of claim 15, wherein the topmost layer is a crystalline oxide layer in direct contact with the second electrode.

### Claim 19 (depends on 15)

The semiconductor device of claim 15, wherein the ferroelectric layers have orthorhombic phase.

### Claim 20 (depends on 15)

The semiconductor device of claim 15, wherein the ferroelectric layers comprise hafnium zirconium oxide.