# US 12,191,388 B2 · Area scaling for VTFET contacts

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- Number: US 12,191,388 B2
- Document ID: US12191388B2
- Status: Granted
- Kind: B2
- Application number: 17/520,812
- Filed: 2021-11-08
- Published: 2023-05-11
- Granted: 2025-01-07
- Earliest claimed: 2021-11-08
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Yann Mignot; Su Chen Fan; Jing Guo; Lijuan Zou
- Web page: https://patentgrep.com/patent/US12191388B2

## CPC

- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Techniques for area scaling of contacts in VTFET devices are provided. In one aspect, a VTFET device includes: a fin(s); a bottom source/drain region at a base of the fin(s); a gate stack alongside the fin(s); a top source/drain region present at a top of the fin(s); a bottom source/drain contact to the bottom source/drain region; and a gate contact to the gate stack, wherein the bottom source drain and gate contacts each includes a top portion having a width W1CONTACT over a bottom portion having a width W2CONTACT, wherein W2CONTACT<W1CONTACT, and wherein a sidewall along the top portion is discontinuous with a sidewall along the bottom portion. The bottom portion having the width W2CONTACT is present alongside the gate stack and the top source/drain region. A method of forming a VTFET device is also provided.

## Claims

### Claim 1

A vertical transport field effect transistor (VTFET) device, comprising:
at least one fin serving as a vertical fin channel;
a bottom source/drain region present at a base of the at least one fin;
a gate stack alongside the at least one fin, wherein the gate stack extends along a vertical sidewall of the at least one fin;
a top source/drain region present at a top of the at least one fin;
an encapsulation layer located on top of and along a vertical side of the gate stack that extends along a vertical sidewall of the at least one fin, wherein the encapsulation layer is located adjacent to the top source/drain region;
a bottom spacer located adjacent to the sidewalls of the at least one fin, wherein the gate stack is in contact with a top surface of the bottom spacer, wherein the encapsulation layer is in contact with the top surface of the bottom spacer;
a bottom source/drain contact to the bottom source/drain region; and
a gate contact to the gate stack, wherein the bottom source drain contact and the gate contact each comprises a single solid structure with a top portion having a width W1CONTACT over a bottom portion having a width W2CONTACT, wherein W2CONTACT<W1CONTACT, and wherein a sidewall along the top portion is discontinuous with a sidewall along the bottom portion.

### Claim 2 (depends on 1)

The VTFET device of claim 1, wherein a step joins the sidewall along the top portion with the sidewall along the bottom portion.

### Claim 3 (depends on 1)

The VTFET device of claim 1,
wherein the bottom spacer is located over the bottom source/drain region.

### Claim 4 (depends on 3)

The VTFET device of claim 3, wherein the encapsulation layer comprises a material selected from the group consisting of: silicon nitride (SiN), silicon-boron-nitride (SiBN), siliconborocarbonitride (SiBCN), silicon oxycarbonitride (SiOCN), and combinations thereof.

### Claim 5 (depends on 3)

The VTFET device of claim 3, wherein portions of the encapsulation layer at the tops of the at least one fin serve as a top spacer.

### Claim 6 (depends on 3)

The VTFET device of claim 3, further comprising:
a first interlayer dielectric (ILD) over the encapsulation layer;
a capping layer disposed on the first ILD; and
a second ILD disposed on the capping layer.

### Claim 7 (depends on 6)

The VTFET device of claim 6, wherein the capping layer comprises a material selected from the group consisting of: SiN, silicon oxynitride (SiON), silicon carbide nitride (SiCN), and combinations thereof.

### Claim 8 (depends on 6)

The VTFET device of claim 6, wherein the bottom portion of the bottom source drain contact having the width W2CONTACT is present in the bottom spacer, the encapsulation layer, and the first ILD, and wherein the top portion of the bottom source drain contact having the width W1CONTACT is present in the second ILD.

### Claim 9 (depends on 6)

The VTFET device of claim 6, wherein the bottom portion of the gate contact having the width W2CONTACT is present in the encapsulation layer, and the first ILD, and wherein the top portion of the gate contact having the width W1CONTACT is present in the second ILD.

### Claim 10 (depends on 1)

The VTFET device of claim 1, wherein W1CONTACT is from about 5 nm to about 15 nm, and wherein W2CONTACT is from about 3 nm to about 10 nm.

### Claim 11 (depends on 1)

The VTFET device of claim 1, further comprising:
a top source/drain contact to the top source/drain region located in between the bottom source/drain contact and the gate contact.

### Claim 12 (depends on 11)

The VTFET device of claim 11, wherein the top source/drain contact overlaps at least a portion of the bottom source/drain contact.

### Claim 13

A vertical transport field effect transistor (VTFET) device, comprising:
at least one fin serving as a vertical fin channel of the VTEFT device;
a bottom source/drain region present at a base of the at least one fin;
a gate stack alongside the at least one fin, wherein the gate stack extends along a vertical sidewall of the at least one fin;
a top source/drain region present at a top of the at least one fin;
an encapsulation layer located on top of and along a vertical side of the gate stack that extends along a vertical sidewall of the at least one fin, wherein the encapsulation layer is located adjacent to the top source/drain region;
a bottom spacer located adjacent to the sidewalls of the at least one fin, wherein the gate stack is in contact with a top surface of the bottom spacer, wherein the encapsulation layer is in contact with the top surface of the bottom spacer;
a bottom source/drain contact to the bottom source/drain region; and
a gate contact to the gate stack, wherein the bottom source drain contact and the gate contact each comprises a single solid structure with a top portion having a width W1CONTACT over a bottom portion having a width W2CONTACT, wherein W2CONTACT<W1CONTACT, and wherein the bottom portion having the width W2CONTACT is present alongside the gate stack and the top source/drain region.

### Claim 14 (depends on 13)

The VTFET device of claim 13, wherein the top portion having a width W1CONTACT is present above the top source/drain region.

### Claim 15 (depends on 13)

The VTFET device of claim 13, wherein a sidewall along the top portion is discontinuous with a sidewall along the bottom portion.

### Claim 16 (depends on 15)

The VTFET device of claim 15, wherein a step joins the sidewall along the top portion with the sidewall along the bottom portion.

### Claim 17 (depends on 13)

The VTFET device of claim 13, further comprising:
a top source/drain contact to the top source/drain region located in between the bottom source/drain contact and the gate contact.

### Claim 18 (depends on 17)

The VTFET device of claim 17, wherein the top source/drain contact overlaps at least a portion of the bottom source/drain contact.

### Claim 19

A method of forming a vertical transport field effect transistor (VTFET) device, the method comprising:
forming a VTFET comprising: at least one fin serving as a vertical fin channel, a bottom source/drain region present at a base of the at least one fin, a bottom spacer is located over the bottom source/drain region, a gate stack alongside the at least one fin, an encapsulation layer disposed over the gate stack, and a top source/drain region present at a top of the at least one fin, wherein the gate stack extends along a vertical sidewall of the at least one fin, wherein the encapsulation layer in in contact with a sidewall of the top source/drain region and a vertical sidewall of the gate stack, wherein the bottom spacer is located adjacent to the sidewalls of the at least one fin, wherein the gate stack is in contact with a top surface of the bottom spacer, wherein the encapsulation layer is in contact with the top surface of the bottom spacer;
depositing a first ILD over the VTFET;
depositing a capping layer on the first ILD;
depositing a second ILD on the capping layer;
forming contact trenches in the second ILD, wherein the contact trenches comprise at least a first contact trench over the bottom source/drain region and a second contact trench over the gate stack;
forming sidewall spacers along sidewalls of the contact trenches;
performing an etch between the sidewall spacers to extend the contact trenches through the capping layer and the first ILD;
removing the sidewall spacers such that each of the contact trenches comprises a top portion having a width W1TRENCH over a bottom portion having a width W2TRENCH, wherein W2TRENCH<W1TRENCH, and wherein a sidewall along the top portion is discontinuous with a sidewall along the bottom portion; and
filling the top portion and the bottom portion of each of the contact trenches with at least one contact metal to form a single solid structure therein.

### Claim 20 (depends on 19)

The method of claim 19, further comprising:
forming a third contact trench in the second ILD over the top source/drain region, wherein the third contact trench overlaps the first contact trench to form a merged contact trench over both the bottom source/drain region and the top source/drain region.