# US 12,191,386 B2 · Power semiconductor device and method of fabricating the same

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- Number: US 12,191,386 B2
- Document ID: US12191386B2
- Status: Granted
- Kind: B2
- Application number: 18/603,723
- Filed: 2024-03-13
- Published: 2024-07-04
- Granted: 2025-01-07
- Earliest claimed: 2020-05-26
- Assignees: Hyundai Mobis Co., Ltd.
- Applicants: Hyundai Mobis Co., Ltd.
- Inventors: Jeong Mok Ha; Hyuk Woo; Sin A Kim; Tae Youp Kim; Ju Hwan Lee; Min Gi Kang; Tae Yang Kim
- Web page: https://patentgrep.com/patent/US12191386B2

## CPC

- H10D 12/031: {of IGBTs}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/635: {having no inversion channels, e.g. vertical accumulation channel FETs [ACCUFET] or normally-on vertical IGFETs}
- H10D 62/105: {by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] (IGFETs having LDD or drain extension regions H10D30/601)}
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 62/159: {Shapes}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/8325: {Silicon carbide}
- H10D 64/112: {comprising multiple field plate segments}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 84/146: {the built-in components being Schottky barrier diodes}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A power semiconductor device includes a semiconductor layer of silicon carbide (SiC), at least one trench that extends in one direction, a gate insulating layer disposed on at least an inner wall of the at least one trench, at least one gate electrode layer disposed on the gate insulating layer, a drift region disposed in the semiconductor layer at least on one side of the at least one gate electrode layer, a well region disposed in the semiconductor layer to be deeper than the at least one gate electrode layer, a source region disposed in the well region, and at least one channel region disposed in the semiconductor layer of one side of the at least one gate electrode layer between the drift region and the source region.

## Claims

### Claim 1

A power semiconductor device comprising:
a first trench recessed into a semiconductor layer in a first direction from a surface of the semiconductor layer and extending in a second direction which is different from the first direction;
a source contact region spaced apart from the first trench in the second direction;
a well region including a first well region which is in contact with the first trench and a second well region which is in contact with the first trench and is spaced apart from the first well region; and
a drift region including a vertical portion of the drift region which is in contact with the first trench and is disposed between the first well region and the second well region;
wherein the vertical portion of the drift region is in contact with the surface of the semiconductor layer.

### Claim 2 (depends on 1)

The power semiconductor device of claim 1,
wherein the source contact region is further extending in a third direction which is perpendicular to the second direction.

### Claim 3 (depends on 1)

The power semiconductor device of claim 1, further comprising:
a first gate insulating layer disposed on an inner wall of the first trench; and
a first gate electrode layer disposed on the first gate insulating layer in the first trench and extending to above the surface of the semiconductor and covering at least a portion of the surface of the semiconductor.

### Claim 4 (depends on 1)

The power semiconductor device of claim 1,
wherein the first direction is perpendicular to the second direction.

### Claim 5 (depends on 1)

The power semiconductor device of claim 1,
wherein the drift region has a first conductivity type, and the well region has a second conductivity type.

### Claim 6 (depends on 5)

The power semiconductor device of claim 5, further comprising:
a source region including a first source region and a second source region and which is in contact with the surface of the semiconductor layer and has the first conductivity type; and
a drain region disposed under the drift region;
wherein the drift region is extending along a bottom surface of the well region,
wherein a portion of a top surface of the source region is the source contact region,
wherein the first source region is disposed in the first well region and is in contacted with the first trench, and
wherein the second source region is disposed in the second well region and is in contacted with the first trench.

### Claim 7 (depends on 6)

The power semiconductor device of claim 6, further comprising:
a well contact region penetrating a portion of the source region, and which is in contact with the surface of the semiconductor layer; and
a source electrode layer disposed on the surface of the semiconductor layer, and which is in contact with the well contact region and the source contact region.

### Claim 8 (depends on 1)

The power semiconductor device of claim 1:
wherein the well region is in contact with the source contact region.

### Claim 9 (depends on 1)

The power semiconductor device of claim 1, further comprising:
a second trench recessed into the semiconductor layer in the first direction from the surface of the semiconductor layer and extending in the second direction and spaced apart from the source contact region in the second direction;
a second gate insulating layer disposed on an inner wall of the second trench;
a second gate electrode disposed on the second gate insulating layer in the second trench and extending to above the surface of the semiconductor and covering at least a portion of the surface of the semiconductor.

### Claim 10

A power semiconductor device comprising:
a plurality of trenches recessed into a semiconductor layer in a first direction from a surface of the semiconductor layer and extending in a second direction which is different from the first direction, and the plurality of trenches is spaced apart from each other in a third direction which is different from the first and the second direction;
a first and a second well regions which surround one portion of a bottom surface and both side surface of each of the plurality of trenches;
a drift region including a vertical portion of the drift region disposed between the first and the second well regions, and the vertical portion of the drift region surrounds another portion of the bottom surface and the both side surface of each of the plurality of trenches; and
a field reduction region which is disposed in the vertical portion of the drift region and surrounds another portion of the bottom surface and the both side surface of each of the plurality of trenches;
wherein the drift region is extending below the vertical portion of the drift region, and is extending below the first and the second well regions, and
wherein the drift region has a first conductivity type, and the first, the second well region and the field reduction region have a second conductivity type.

### Claim 11 (depends on 10)

The power semiconductor device of the claim 10, further comprising:
a source region including a first source region disposed in the first well region and a second source region disposed in the second well region;
wherein the source region is in contact with the surface of the semiconductor layer, and has the first conductivity type.

### Claim 12 (depends on 11)

The power semiconductor device of the claim 11:
wherein the source region is disposed from the surface of the semiconductor layer to a first depth,
wherein the plurality of the trenches is disposed from the surface of the semiconductor layer to a second depth, and
wherein the first depth is shallower than the second depth.

### Claim 13 (depends on 11)

The power semiconductor device of the claim 11,
wherein the source region is disposed between the plurality of the trenches along the third direction.

### Claim 14 (depends on 10)

The power semiconductor device of the claim 10, further comprising:
a gate insulating layer disposed in inner walls of each of the plurality of the trenches and disposed on the surface of the semiconductor layer between the plurality of the trenches; and
a gate electrode layer disposed on the gate insulating layer in each of the plurality of the trenches and extending above the surface of the semiconductor layer and covering at least of a portion of the surface of the semiconductor layer.

### Claim 15 (depends on 10)

The power semiconductor device of the claim 10:
wherein the second direction is perpendicular to the first direction, and the third direction is perpendicular to the first and the second direction.