# US 12,191,380 B2 · Semiconductor device and method

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- Number: US 12,191,380 B2
- Document ID: US12191380B2
- Status: Granted
- Kind: B2
- Application number: 17/814,185
- Filed: 2022-07-21
- Published: 2022-11-10
- Granted: 2025-01-07
- Earliest claimed: 2020-06-11
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Ssu-Yu Liao; Tsu-Hui Su; Chun-Hsiang Fan; Yu-Wen Wang; Ming-Hsi Yeh; Kuo-Bin Huang
- Web page: https://patentgrep.com/patent/US12191380B2

## CPC

- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/751: {having composition variations in the channel regions}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/853: {comprising FinFETs}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3462: {Nanowires}
- H10D 30/0194: {the stacked channels having different properties}
- H10D 30/503: {having non-rectangular cross-sections}
- H10D 30/506: {having different thicknesses, sizes or shapes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Methods for improving profiles of channel regions in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a semiconductor fin over a semiconductor substrate, the semiconductor fin including germanium, a germanium concentration of a first portion of the semiconductor fin being greater than a germanium concentration of a second portion of the semiconductor fin, a first distance between the first portion and a major surface of the semiconductor substrate being less than a second distance between the second portion and the major surface of the semiconductor substrate; and trimming the semiconductor fin, the first portion of the semiconductor fin being trimmed at a greater rate than the second portion of the semiconductor fin.

## Claims

### Claim 1

A method comprising:
forming a semiconductor fin over a semiconductor substrate, the semiconductor fin comprising a silicon germanium portion and a silicon portion, wherein a germanium concentration of a lower portion of the silicon germanium portion of the semiconductor fin is greater than a germanium concentration of an upper portion of the silicon germanium portion of the semiconductor fin; and
trimming the semiconductor fin, wherein the lower portion of the silicon germanium portion of the semiconductor fin is trimmed at a greater rate than the upper portion of the silicon germanium portion of the semiconductor fin, wherein trimming the semiconductor fin exposes a first horizontal surface of the silicon portion of the semiconductor fin.

### Claim 2 (depends on 1)

The method of claim 1, wherein a first angle between a sidewall of the silicon germanium portion of the semiconductor fin and a major surface of the semiconductor substrate before trimming the semiconductor fin is different from a second angle between the sidewall of the silicon germanium portion of the semiconductor fin and the major surface of the semiconductor substrate after trimming the semiconductor fin.

### Claim 3 (depends on 1)

The method of claim 1, wherein a ratio of a trimming rate of the lower portion of the silicon germanium portion of the semiconductor fin to a trimming rate of the upper portion of the silicon germanium portion of the semiconductor fin is from 1 to 3.

### Claim 4 (depends on 1)

The method of claim 1, wherein trimming the semiconductor fin comprises exposing the semiconductor fin to an oxidant.

### Claim 5 (depends on 1)

The method of claim 1, wherein trimming the semiconductor fin comprises exposing the semiconductor fin to an oxidant, then exposing the semiconductor fin to an alkaline or an acid in a cyclical process.

### Claim 6 (depends on 1)

The method of claim 1, further comprising forming a shallow trench isolation region surrounding at least a portion of the semiconductor fin, wherein the semiconductor fin is trimmed after forming the shallow trench isolation region.

### Claim 7 (depends on 1)

The method of claim 1, further comprising forming a shallow trench isolation region surrounding at least a portion of the semiconductor fin, wherein the semiconductor fin is trimmed before forming the shallow trench isolation region.

### Claim 8 (depends on 1)

The method of claim 1, further comprising:
forming a dummy gate over the semiconductor fin; and
after trimming the semiconductor fin, removing the dummy gate to expose the semiconductor fin.

### Claim 9

A method comprising:
forming a multi-layer stack on a semiconductor substrate;
etching the multi-layer stack and the semiconductor substrate to form a nanostructure, the nanostructure comprising a fin-shaped region comprising silicon, a first channel region on the fin-shaped region and comprising silicon germanium, and a second channel region on the first channel region and comprising silicon germanium, wherein the fin-shaped region comprises first straight sidewalls disposed at a first angle with respect to a major surface of the semiconductor substrate after etching the multi-layer stack and the semiconductor substrate;
forming a shallow trench isolation region surrounding the first straight sidewalls of the fin-shaped region; and
trimming the first channel region and the second channel region, wherein the first channel region comprises second straight sidewalls above a top surface of the shallow trench isolation region and disposed at a second angle with respect to the major surface of the semiconductor substrate after trimming the first channel region and the second channel region, the second angle being closer to perpendicular than the first angle, wherein fin-shaped region comprising silicon comprises third straight sidewalls below the top surface of the shallow trench isolation region and disposed at a third angle with respect to the major surface of the semiconductor substrate, the third angle being further from perpendicular than the second angle.

### Claim 10 (depends on 9)

The method of claim 9, wherein the first channel region has a higher germanium concentration than the second channel region.

### Claim 11 (depends on 9)

The method of claim 9, wherein the first channel region is trimmed at a rate greater than the second channel region.

### Claim 12 (depends on 9)

The method of claim 9, wherein trimming the first channel region and the second channel region comprises exposing the first channel region and the second channel region to an oxidant, then exposing the first channel region and the second channel region to an alkaline or an acid in a cyclical process.

### Claim 13 (depends on 9)

The method of claim 9, wherein trimming the first channel region and the second channel region comprises exposing the first channel region and the second channel region to an oxidant.

### Claim 14 (depends on 9)

The method of claim 9, wherein the second straight sidewalls of the first channel region are disposed at a fourth angle with respect to the major surface of the semiconductor substrate after forming the nanostructure and before trimming the first channel region, wherein the second angle is closer to perpendicular than the fourth angle.

### Claim 15

A method comprising:
forming a first semiconductor layer on a semiconductor substrate, the first semiconductor layer having a first germanium concentration;
forming a second semiconductor layer on the first semiconductor layer, the second semiconductor layer comprising silicon;
forming a third semiconductor layer on the first semiconductor layer, the third semiconductor layer having a second germanium concentration less than the first germanium concentration;
etching the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the semiconductor substrate to form a first channel region, a second channel region, a third channel region, and a fin-shaped region, respectively, the third channel region being over and aligned with the first channel region, the second channel region being horizontally spaced apart from the first channel region; and
trimming the first channel region and the third channel region, wherein a first angle between a sidewall of the first channel region and a major surface of the semiconductor substrate after trimming the first channel region and the third channel region is closer to perpendicular than a second angle between the sidewall of the first channel region and the major surface of the semiconductor substrate before trimming the first channel region and the third channel region, wherein after trimming, a third angle between a sidewall of the second channel region and the major surface of the semiconductor substrate is further from perpendicular than the second angle.

### Claim 16 (depends on 15)

The method of claim 15, wherein a first width of the first channel region is greater than a second width of the third channel region before trimming the first channel region and the third channel region, and wherein a third width of the first channel region is equal to a fourth width of the third channel region after trimming the first channel region and the third channel region.

### Claim 17 (depends on 15)

The method of claim 15, wherein the first channel region and the third channel region have trapezoidal shapes in a cross-sectional view before trimming the first channel region and the third channel region, and wherein the first channel region and the third channel region have rectangular shapes in the cross-sectional view after trimming the first channel region and the third channel region.

### Claim 18 (depends on 15)

The method of claim 15, wherein a first trim rate of the first channel region is greater than a second trim rate of the third channel region.

### Claim 19 (depends on 15)

The method of claim 15, wherein trimming the first channel region and the third channel region comprises exposing the first channel region and the third channel region to an oxidant, then exposing the first channel region and the third channel region to an alkaline or an acid in a cyclical process.

### Claim 20 (depends on 15)

The method of claim 15, wherein the first semiconductor layer and the third semiconductor layer are formed with gradient germanium concentrations that decrease with increasing distance from the semiconductor substrate.