# US 12,191,379 B2 · Multi-gate semiconductor device with inner spacer and fabrication method thereof

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- Number: US 12,191,379 B2
- Document ID: US12191379B2
- Status: Granted
- Kind: B2
- Application number: 17/371,968
- Filed: 2021-07-09
- Published: 2023-01-12
- Granted: 2025-01-07
- Earliest claimed: 2021-07-09
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Bone-Fong Wu; Chih-Hao Yu; Chia-Pin Lin
- Web page: https://patentgrep.com/patent/US12191379B2

## CPC

- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/0195: {forming inner spacers between adjacent channels, e.g. changing their shapes or sizes}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/507: {characterised by inner spacers between adjacent channels}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/01: Manufacture or treatment
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/679: {comprising air gaps}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/364: {of IGFETs}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A method of manufacturing a semiconductor device includes forming a fin structure in which first semiconductor layers and second semiconductor layers are alternatively stacked, the first and second semiconductor layers having different material compositions; forming a sacrificial gate structure over the fin structure; forming a gate spacer on sidewalls of the sacrificial gate structure; etching a source/drain (S/D) region of the fin structure, which is not covered by the sacrificial gate structure and the gate spacer, thereby forming an S/D trench; laterally etching the first semiconductor layers through the S/D trench, thereby forming recesses; selectively depositing an insulating layer on surfaces of the first and second semiconductor layers exposed in the recesses and the S/D trench, but not on sidewalls of the gate spacer; and growing an S/D epitaxial feature in the S/D trench, thereby trapping air gaps in the recesses.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, comprising:
forming a fin structure in which first semiconductor layers and second semiconductor layers are alternatively stacked, the first and second semiconductor layers having different material compositions;
forming a sacrificial gate structure over the fin structure;
forming a gate spacer on sidewalls of the sacrificial gate structure;
etching a source/drain (S/D) region of the fin structure, which is not covered by the sacrificial gate structure and the gate spacer, thereby forming an S/D trench;
laterally etching the first semiconductor layers through the S/D trench, thereby forming recesses;
selectively depositing an insulating layer on surfaces of the first and second semiconductor layers exposed in the recesses and the S/D trench, but not on sidewalls of the gate spacer;
performing an anisotropic etching process to remove at least some vertical portions of the insulating layer from the S/D trench, wherein other portions of the insulating layer in the recesses remain; and
growing an S/D epitaxial feature in the S/D trench, thereby trapping air gaps in the recesses.

### Claim 2 (depends on 1)

The method of claim 1, wherein the air gaps are laterally between the S/D epitaxial feature and the insulating layer.

### Claim 3 (depends on 1)

The method of claim 1, wherein the insulating layer has a dielectric constant higher than the gate spacer.

### Claim 4 (depends on 1)

The method of claim 1, wherein the insulating layer comprises silicon, oxygen, carbon, and nitrogen.

### Claim 5 (depends on 1)

The method of claim 1, wherein a portion of the insulating layer in the recesses is in contact with lateral ends of the first semiconductor layers, further comprising:
performing an etching process to reduce a thickness of the portion of the insulating layer.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
removing the sacrificial gate structure, thereby forming a gate trench; and
etching the first semiconductor layers from the gate trench, thereby exposing a portion of the insulating layer in the gate trench, wherein the etching of the first semiconductor layers also reduces a thickness of the portion of the insulating layer.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
removing the sacrificial gate structure, thereby forming a gate trench;
performing a first etching process, thereby removing the first semiconductor layers from the gate trench and exposing a portion of the insulating layer in the gate trench; and
performing a second etching process to reduce a thickness of the portion of the insulating layer.

### Claim 8 (depends on 1)

The method of claim 1, wherein the growing of the S/D epitaxial feature includes controlling a growth rate of the S/D epitaxial feature, such that the S/D epitaxial feature has concave surfaces exposed in the air gaps and extending away from lateral ends of the first semiconductor layers.

### Claim 9 (depends on 1)

The method of claim 1, wherein the growing of the S/D epitaxial feature includes controlling a growth rate of the S/D epitaxial feature, such that the S/D epitaxial feature has convex surfaces exposed in the air gaps and extending towards lateral ends of the first semiconductor layers.

### Claim 10 (depends on 1)

The method of claim 1, wherein the insulating layer comprises a metal oxide.

### Claim 11

A method of manufacturing a semiconductor device, comprising:
forming a stack of first type and second type epitaxial layers on a semiconductor substrate, the first type and second type epitaxial layers having different material compositions and being alternatingly disposed in a vertical direction;
patterning the stack to form a fin structure;
forming a sacrificial gate structure over the fin structure;
removing at least the first type epitaxial layers from a source/drain (S/D) region of the fin structure, which is not covered by the sacrificial gate structure;
forming an insulating layer on lateral ends of the first type epitaxial layers;
forming an S/D epitaxial feature in contact with the insulating layer and the second type epitaxial layers, wherein the insulating layer interposes the S/D epitaxial feature and the first type epitaxial layers, and wherein the S/D epitaxial feature traps air gaps laterally between the S/D epitaxial feature and the insulating layer;
removing the sacrificial gate structure and the first type epitaxial layers, resulting in a gate trench; and
partially etching a portion of the insulating layer exposed in the gate trench.

### Claim 12 (depends on 11)

The method of claim 11, wherein the insulating layer has a dielectric constant larger than 5.

### Claim 13 (depends on 11)

The method of claim 11, wherein the insulating layer includes silicon carbon oxynitride.

### Claim 14 (depends on 11)

The method of claim 11, wherein after the partially etching of the portion of the insulating layer, the portion of the insulating layer exposed in the gate trench has a thickness less than other portions of the insulating layer in contact with the second type epitaxial layers.

### Claim 15 (depends on 11)

The method of claim 11, further comprising:
forming a metal gate stack in the gate trench, wherein the insulating layer interposes the metal gate stack and the air gaps.

### Claim 16 (depends on 11)

The method of claim 11, further comprising:
forming a gate spacer on sidewalls of the sacrificial gate structure, wherein a portion of the gate spacer is exposed in the air gaps.

### Claim 17

A method of manufacturing a semiconductor device, comprising:
forming a fin structure in which first semiconductor layers and second semiconductor layers are alternatively stacked, the first and second semiconductor layers having different material compositions;
forming a sacrificial gate structure over the fin structure;
forming a gate spacer on sidewalls of the sacrificial gate structure;
etching a region of the fin structure not covered by the sacrificial gate structure and the gate spacer, thereby forming a trench;
laterally etching the first semiconductor layers through the trench, thereby forming recesses;
depositing an insulating layer on surfaces of the first and second semiconductor layers exposed in the recesses;
growing an epitaxial feature in the trench, thereby trapping at least an air gap in one of the recesses;
removing the sacrificial gate structure, thereby forming a gate trench;
removing the first semiconductor layers from the gate trench to expose a first portion of the insulating layer in the gate trench; and
forming a metal gate stack in the gate trench and in contact with the first portion of the insulating layer,
wherein the insulating layer includes a second portion in contact with the epitaxial feature, and a thickness of the second portion is larger than a thickness of the first portion.

### Claim 18 (depends on 17)

The method of claim 17, wherein the second portion of the insulating layer extends vertically along a sidewall of the epitaxial feature.

### Claim 19 (depends on 17)

The method of claim 17, wherein the air gap has a dome shape.

### Claim 20 (depends on 17)

The method of claim 17, wherein a ratio of a dielectric constant of the insulating layer over a dielectric constant of the gate spacer ranges from about 1.5 to about 3.