# US 12,191,377 B2 · Method for forming a semiconductor structure

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- Number: US 12,191,377 B2
- Document ID: US12191377B2
- Status: Granted
- Kind: B2
- Application number: 17/560,222
- Filed: 2021-12-22
- Published: 2023-05-04
- Granted: 2025-01-07
- Earliest claimed: 2021-11-03
- Assignees: United Semiconductor (Xiamen) Co., Ltd.
- Applicants: United Semiconductor (Xiamen) Co., Ltd.
- Inventors: Jun Wu; Shih-Hsien Huang; Wen Yi Tan; Feng Gao
- Web page: https://patentgrep.com/patent/US12191377B2

## CPC

- H10D 30/027: {of lateral single-gate IGFETs}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10D 30/0223: {having source and drain regions or source and drain extensions self-aligned to sides of the gate}
- H10P 14/6334: {using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329)}
- H10P 14/6516: {of treatments performed after formation of the materials}
- H10P 14/6529: {by exposure to a gas or vapour}
- H10P 14/6682: {the compound being a silane, e.g. disilane, methylsilane or chlorosilane}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 50/283: {by chemical means}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for forming a semiconductor structure includes forming a gate structure on a substrate, performing a deposition process to form a nitride layer to cover the substrate and the gate structure, performing an in-situ annealing process to the nitride layer, and performing an anisotropic etching process to the nitride layer after the in-situ annealing process to form a spacer on a sidewall of the gate structure.

## Claims

### Claim 1

A method for forming a semiconductor structure, comprising:
forming a gate structure on a substrate, wherein the gate structure comprises:
an interfacial layer on the substrate;
a high-k dielectric layer on the interfacial layer;
a polysilicon layer on the high-k dielectric layer; and
a hard mask layer on the polysilicon layer;
performing a deposition process to form a nitride layer to cover the substrate and the gate structure, wherein a process temperature of the deposition process is between 600° C. and 650° C.;
performing an in-situ annealing process to the nitride layer, wherein a process temperature of the in-situ annealing process is higher than 700° C.; and
performing an anisotropic etching process to the nitride layer after the in-situ annealing process to form a spacer on the substrate and covering sidewalls of the interfacial layer, the high-k dielectric layer, the polysilicon layer and the hard mask layer of the gate structure, wherein a bottom width of a portion of the spacer on the sidewall of the interfacial layer is 1.1 times of a middle width of another portion of the spacer on the sidewall of the polysilicon layer.

### Claim 2 (depends on 1)

The method for forming a semiconductor structure according to claim 1, wherein the deposition process is a low pressure chemical vapor deposition (LPCVD) process using dichlorosilane (DCS) and ammonia (NH3) as source gases to form the nitride layer.

### Claim 3 (depends on 1)

The method for forming a semiconductor structure according to claim 1, wherein the in-situ annealing process is performed in a nitrogen (N2) atmosphere.

### Claim 4 (depends on 1)

The method for forming a semiconductor structure according to claim 1, wherein the process temperature of the in-situ annealing process is higher than 700° C. and lower than 800° C.

### Claim 5 (depends on 4)

The method for forming a semiconductor structure according to claim 4, wherein the process temperature of the in-situ annealing process is between 750° C. and 770° C.

### Claim 6 (depends on 1)

The method for forming a semiconductor structure according to claim 1, wherein a process time of the in-situ annealing process is between 30 and 120 minutes.

### Claim 7 (depends on 1)

The method for forming a semiconductor structure according to claim 1, wherein a thickness of the nitride layer is between 80 and 100 Å.

### Claim 8 (depends on 1)

The method for forming a semiconductor structure according to claim 1, wherein the deposition process and the in-situ annealing process are performed by a same low pressure furnace equipment.

### Claim 9 (depends on 1)

The method for forming a semiconductor structure according to claim 1, wherein the anisotropic etching process comprises using O2, CH2F2 and CHF3.

### Claim 10 (depends on 1)

The method for forming a semiconductor structure according to claim 1, further comprising forming a source/drain region in the substrate and adjacent to the spacer.