# US 12,191,375 B2 · Ferroelectric channel field effect transistor

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,191,375 B2
- Document ID: US12191375B2
- Status: Granted
- Kind: B2
- Application number: 18/361,331
- Filed: 2023-07-28
- Published: 2023-11-23
- Granted: 2025-01-07
- Earliest claimed: 2020-05-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Gerben Doornbos; Marcus Johannes Henricus van Dal; Georgios Vellianitis
- Web page: https://patentgrep.com/patent/US12191375B2

## CPC

- H10D 64/689: {having ferroelectric layers}
- H10B 51/30: characterised by the memory core region
- H10D 30/0415: {of FETs having ferroelectric gate insulators}
- H10D 30/6215: {having multiple independently-addressable gate electrodes}
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 62/40: Crystalline structures
- H10D 62/854: further characterised by the dopants
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a ferroelectric structure including a channel region and a source/drain region, a gate dielectric layer disposed over the channel region of the ferroelectric structure, a gate electrode disposed on the gate dielectric layer, and a source/drain contact disposed on the source/drain region of the ferroelectric structure. The ferroelectric structure includes gallium nitride, indium nitride, or indium gallium nitride. The ferroelectric structure is doped with a dopant.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a III-V compound semiconductor layer over the substrate and comprising a first source/drain region, a second source/drain region, and a channel region sandwiched between the first source/drain region and the second source/drain region;
a first source/drain contact disposed over and in contact with the first source/drain region;
a second source/drain contact disposed over and in contact with the second source/drain region;
a gate dielectric layer continuously disposed along a sidewall of the first source/drain contact, a top surface of the channel region, and a sidewall of the second source/drain contact; and
a gate electrode disposed over the gate dielectric layer and spaced apart from the sidewall of the first source/drain contact, the top surface of the channel region, and the sidewall of the second source/drain contact by the gate dielectric layer,
wherein the channel region is doped with a dopant to exhibit ferroelectric property,
wherein the first source/drain region and the second source/drain region are free of the dopant.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the III-V compound semiconductor layer comprises gallium nitride, indium nitride, or indium gallium nitride.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the dopant comprises scandium (Sc).

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the channel region comprises a wurtzite crystalline structure.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein a horizontal surface of the channel region comprises a (0001) crystalline face.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the gate dielectric layer comprises hafnium oxide, silicon oxide, aluminum oxide, or aluminum nitride.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the first source/drain contact and the second source/drain contact comprise tungsten, nickel, tantalum, titanium, aluminum, copper, cobalt, tantalum nitride, titanium nitride, or ruthenium.

### Claim 8

A semiconductor device, comprising:
a ferroelectric structure comprising a first source/drain region, a second source/drain region, and a channel region sandwiched between the first source/drain region and the second source/drain region along a direction;
a front gate dielectric layer disposed over the channel region;
a front gate electrode disposed over the front gate dielectric layer;
a first source/drain contact over the first source/drain region;
a second source/drain contact over the second source/drain region;
a back gate dielectric layer disposed below and in contact with a bottom surface of the ferroelectric structure; and
a back gate electrode disposed below and in contact with a bottom surface of the back gate dielectric layer,
wherein the front gate dielectric layer comprises a first width along the direction and the back gate dielectric layer comprises a second width along the direction,
wherein the first width is greater than the second width.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the back gate dielectric layer is disposed directly below the front gate dielectric layer.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein the back gate dielectric layer is off-centered such that a geometric center line of the front gate electrode is not aligned with a geometric center line of the back gate electrode.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, wherein the ferroelectric structure comprises gallium nitride, indium nitride, or indium gallium nitride.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the ferroelectric structure comprises scandium as a dopant.

### Claim 13 (depends on 8)

The semiconductor device of claim 8,
wherein the front gate dielectric layer comprises a first thickness,
wherein the back gate dielectric layer comprises a second thickness greater than the first thickness.

### Claim 14 (depends on 8)

The semiconductor device of claim 8, wherein the front gate dielectric layer and the back gate dielectric layer comprise hafnium oxide, silicon oxide, aluminum oxide, aluminum nitride.

### Claim 15 (depends on 8)

The semiconductor device of claim 8, wherein, along the direction, the ferroelectric structure is sandwiched between two isolation structures.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the two isolation structures comprise silicon oxide.

### Claim 17

A semiconductor device, comprising:
a ferroelectric structure comprising a first source/drain region, a second source/drain region, and a channel region sandwiched between the first source/drain region and the second source/drain region along a direction;
a front gate dielectric layer disposed over the channel region;
a front gate electrode disposed over the front gate dielectric layer;
a first source/drain contact over the first source/drain region;
a second source/drain contact over the second source/drain region;
a back gate dielectric layer disposed below and in contact with a bottom surface of the ferroelectric structure; and
a back gate electrode disposed below and in contact with a bottom surface of the back gate dielectric layer,
wherein the ferroelectric structure comprises III-V semiconductor and a dopant,
wherein the front gate dielectric layer comprises a first thickness,
wherein the back gate dielectric layer comprises a second thickness greater than the first thickness.

### Claim 18 (depends on 17)

The semiconductor device of claim 17,
wherein the III-V semiconductor comprise gallium nitride, indium nitride, or indium gallium nitride,
wherein the dopant comprises scandium (Sc).

### Claim 19 (depends on 17)

The semiconductor device of claim 17,
wherein the front gate dielectric layer comprises a first width along the direction and the back gate dielectric layer comprises a second width along the direction,
wherein the first width is greater than the second width.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein the back gate dielectric layer is disposed directly below the front gate dielectric layer.