# US 12,191,374 B2 · Semiconductor device with reduced flicker noise

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- Number: US 12,191,374 B2
- Document ID: US12191374B2
- Status: Granted
- Kind: B2
- Application number: 18/323,457
- Filed: 2023-05-25
- Published: 2023-09-21
- Granted: 2025-01-07
- Earliest claimed: 2018-07-26
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Hsin-Li Cheng; Liang-Tai Kuo; Yu-Chi Chang
- Web page: https://patentgrep.com/patent/US12191374B2

## CPC

- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 30/022: {having lightly-doped source or drain extensions selectively formed at the sides of the gates}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 64/01338: {with a treatment, e.g. annealing, after the formation of the conductor}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10P 30/40: into insulating materials
- H10P 32/20: Diffusion for doping of insulating layers
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

In some embodiments, a semiconductor device is provided. The semiconductor device includes a gate electrode disposed on a substrate. Source/drain regions are disposed on or within the substrate along opposing sides of the gate electrode. A noise reducing component is arranged along an upper surface of the gate electrode and/or along an upper surface of the substrate over the source/drain regions. A cap layer covers the upper surface of the gate electrode and/or the upper surface of the substrate over the source/drain regions. An inter-level dielectric (ILD) is disposed over and along one or more sidewalls of the cap layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a gate electrode disposed on a substrate;
source/drain regions disposed on or within the substrate along opposing sides of the gate electrode;
a noise reducing component arranged along an upper surface of the gate electrode and/or along an upper surface of the substrate over the source/drain regions;
a cap layer covering the upper surface of the gate electrode and/or the upper surface of the substrate over the source/drain regions; and
an inter-level dielectric (ILD) disposed over and along one or more sidewalls of the cap layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the cap layer comprises a lower horizontally extending segment and an upper horizontally extending segment, the upper horizontally extending segment coupled to the lower horizontally extending segment by way of a vertically extending segment.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the cap layer has an upper surface protruding outward from a sidewall of the cap layer, the upper surface being directly over one of the source/drain regions.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising:
a contact etch stop layer arranged on the cap layer, the contact etch stop layer having a stepped lower surface facing the substrate.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising:
a conductive contact electrically coupled to one of the source/drain regions, wherein the cap layer comprises an outermost sidewall that faces the conductive contact and that is laterally separated from the conductive contact by a non-zero distance.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the noise reducing component comprises one or more of fluorine, chlorine, and hydrogen.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, further comprising:
a dielectric isolation structure disposed within a trench formed by sidewalls of the substrate, wherein the cap layer continuously extends from over the gate electrode to an outermost sidewall that is directly over the dielectric isolation structure.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the cap layer comprises silicon nitride.

### Claim 9

A semiconductor device, comprising:
a gate structure over a substrate;
source/drain regions disposed on opposing sides of the gate structure;
a noise reducing component arranged along tops of one or more of the gate structure and the source/drain regions;
a cap layer covering the noise reducing component; and
an inter-level dielectric (ILD) disposed over the cap layer and extending laterally past an outermost sidewall of the cap layer.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the cap layer comprises a lower horizontally extending segment protruding outward from a sidewall of the cap layer.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein the cap layer comprises a first sidewall disposed on a first side of the gate structure and a second sidewall disposed on the first side of the gate structure, the first sidewall and the second sidewall facing away from the gate structure.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, wherein the noise reducing component is arranged along an upper surface of the substrate directly below the cap layer and laterally outside of the cap layer.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, wherein the noise reducing component is arranged along the tops of the gate structure and the source/drain regions.

### Claim 14 (depends on 9)

The semiconductor device of claim 9, wherein the noise reducing component is fluorine.

### Claim 15

A semiconductor device, comprising:
a gate electrode disposed on a substrate;
source/drain regions disposed on opposing sides of the gate electrode;
a noise reducing component arranged within the gate electrode and the source/drain regions; and
a cap layer covering the noise reducing component, wherein the cap layer is disposed over a top of the gate electrode and has an upper surface that is below the top of the gate electrode.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the cap layer comprises an “L” shaped segment laterally outside of the gate electrode.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein the cap layer has an outermost sidewall having a first height, the first height being less than a second height of the gate electrode.

### Claim 18 (depends on 15)

The semiconductor device of claim 15, wherein the gate electrode extends past an outermost sidewall of the cap layer along a first direction and wherein the cap layer extends past an outermost sidewall of the gate electrode along a second direction, the second direction being perpendicular to the first direction.

### Claim 19 (depends on 15)

The semiconductor device of claim 15, wherein the cap layer extends to a distance of greater than 0.2 microns past an outermost sidewall of the gate electrode.

### Claim 20 (depends on 15)

The semiconductor device of claim 15, wherein the gate electrode is arranged over an active area of the substrate, the cap layer having a greater width than the active area, as viewed in a cross-sectional view.