# US 12,191,371 B2 · Field effect transistor with disabled channels and method

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- Number: US 12,191,371 B2
- Document ID: US12191371B2
- Status: Granted
- Kind: B2
- Application number: 17/736,036
- Filed: 2022-05-03
- Published: 2023-05-04
- Granted: 2025-01-07
- Earliest claimed: 2021-11-04
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yu-Xuan Huang; Hou-Yu Chen; Jin Cai; Zhi-Chang Lin; Chih-Hao Wang
- Web page: https://patentgrep.com/patent/US12191371B2

## CPC

- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10P 32/00: Diffusion of dopants within, into or out of wafers, substrates or parts of devices (during formation of materials H10P14/00)
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 62/364: {of IGFETs}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A device includes a vertical stack of semiconductor nanostructures, a gate structure, a first epitaxial region and a dielectric structure. The gate structure wraps around the semiconductor nanostructures. The first epitaxial region laterally abuts a first semiconductor nanostructure of the semiconductor nanostructures. The dielectric structure laterally abuts a second semiconductor nanostructure of the semiconductor nanostructures and vertically abuts the first epitaxial region.

## Claims

### Claim 1

A method, comprising:
forming a first device on a substrate, including:
forming a vertical stack of semiconductor layers over the substrate;
forming a sacrificial gate structure that wraps around a portion of the vertical stack;
forming first openings adjacent to the sacrificial gate structure by recessing the vertical stack;
forming a first epitaxial layer in the first openings;
forming a second epitaxial layer in the first openings on the first epitaxial layer;
removing the sacrificial gate structure;
forming a gate structure that wraps around the semiconductor layers;
exposing the first epitaxial layer by thinning the substrate from a backside of the substrate;
forming second openings by recessing the first epitaxial layer; and
forming a dielectric structure in the second openings.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first and second epitaxial layers are formed in situ.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first epitaxial layer is formed substantially free of dopants.

### Claim 4 (depends on 1)

The method of claim 1, wherein dopant concentration in the second epitaxial layer is higher than that in the first epitaxial layer.

### Claim 5 (depends on 1)

The method of claim 1, wherein the removing the sacrificial gate structure precedes the removing the first epitaxial layer.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
disabling at least one of the semiconductor layers by the forming the dielectric structure.

### Claim 7 (depends on 6)

The method of claim 6, further comprising:
disabling semiconductor layers of a second device on the substrate, the second device having a different number of semiconductor layers disabled than are disabled in the first device.

### Claim 8 (depends on 1)

The method of claim 1, wherein the forming a dielectric structure includes:
forming a liner layer; and
forming a core layer on the liner layer.

### Claim 9 (depends on 1)

The method of claim 1, further comprising forming a dielectric layer from the backside, the dielectric layer covering the dielectric structure.

### Claim 10 (depends on 1)

The method of claim 1, wherein the forming second openings includes:
forming the second openings to a level that has an offset from a topmost disabled sheet of the semiconductor layers, the offset being in a range of about 2 nanometers to about 5 nanometers.

### Claim 11

A device, comprising:
a vertical stack of semiconductor nanostructures;
a gate structure that wraps around the semiconductor nanostructures;
a first epitaxial region laterally abutting a first semiconductor nanostructure of the semiconductor nanostructures; and
a dielectric structure that laterally abuts a second semiconductor nanostructure of the semiconductor nanostructures and vertically abuts the first epitaxial region.

### Claim 12 (depends on 11)

The device of claim 11, wherein the dielectric structure includes:
a liner layer on surfaces of the second semiconductor nanostructure and the first epitaxial region; and
a core layer on the liner layer.

### Claim 13 (depends on 12)

The device of claim 12, wherein the liner layer has thickness in a range of about 3 nanometers to about 5 nanometers.

### Claim 14 (depends on 12)

The device of claim 12, wherein a first cross-sectional profile of the liner layer is U-shaped.

### Claim 15 (depends on 14)

The device of claim 14, wherein a second cross-sectional profile of the liner layer includes tapered corners, the second cross-sectional profile being substantially perpendicular to the first cross-sectional profile.

### Claim 16 (depends on 12)

The device of claim 12, further comprising:
a dielectric layer in contact with the liner layer, the core layer and the gate structure.

### Claim 17 (depends on 11)

The device of claim 11, further comprising:
an inner spacer laterally between the gate structure and the dielectric structure.

### Claim 18

A device, comprising:
a first device including:
a first vertical stack of first nanostructures;
a first gate structure that wraps around the first nanostructures;
a first epitaxial region that laterally abuts the first nanostructures; and
a first dielectric structure that laterally abuts the first nanostructures and extends to a first level above a first number of the first nanostructures; and
a second device laterally offset from the first device, the second device including:
a second vertical stack of second nanostructures;
a second gate structure that wraps around the second nanostructures;
a second epitaxial region that laterally abuts the second nanostructures; and
a second dielectric structure that laterally abuts the second nanostructures and extends to a second level above a second number of the second nanostructures, the second number being different than the first number.

### Claim 19 (depends on 18)

The device of claim 18, wherein:
the first epitaxial region abuts at least three of the first nanostructures; and
the second epitaxial region abuts two or fewer of the second nanostructures.

### Claim 20 (depends on 18)

The device of claim 18, further comprising:
backside circuitry electrically connected to the first epitaxial region through the first dielectric structure.