# US 12,191,370 B2 · Semiconductor device with tunable channel layer usage and methods of fabrication thereof

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- Number: US 12,191,370 B2
- Document ID: US12191370B2
- Status: Granted
- Kind: B2
- Application number: 17/714,528
- Filed: 2022-04-06
- Published: 2023-06-15
- Granted: 2025-01-07
- Earliest claimed: 2021-12-14
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Bo-Yu Lai; Wei-Yang Lee; Ming-Lung Cheng; Chia-Pin Lin; Yuan-Ching Peng
- Web page: https://patentgrep.com/patent/US12191370B2

## CPC

- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 30/0194: {the stacked channels having different properties}
- H10D 30/504: {wherein the stacked channels have different properties}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method includes forming a stack of channel layers and sacrificial layers on a substrate. The channel layers and the sacrificial layers have different material compositions and being alternatingly disposed in a vertical direction. The method further includes patterning the stack to form a semiconductor fin, forming an isolation feature on sidewalls of the semiconductor fin, recessing the semiconductor fin, thereby forming a source/drain recess, such that a recessed top surface of the semiconductor fin is below a top surface of the isolation feature, growing a base epitaxial layer from the recessed top surface of the semiconductor fin, depositing an insulation layer in the source/drain recess, and forming an epitaxial feature in the source/drain recess, wherein the epitaxial feature is above the insulation layer. The insulation layer is above the base epitaxial layer and above a bottommost channel layer.

## Claims

### Claim 1

A method, comprising:
forming a stack of channel layers and sacrificial layers on a substrate, the channel layers and the sacrificial layers having different material compositions and being alternatingly disposed in a vertical direction;
patterning the stack to form a semiconductor fin;
forming an isolation feature on sidewalls of the semiconductor fin;
recessing the semiconductor fin, thereby forming a source/drain recess, such that a recessed top surface of the semiconductor fin is below a top surface of the isolation feature;
growing a base epitaxial layer from the recessed top surface of the semiconductor fin;
depositing an insulation layer in the source/drain recess, wherein the insulation layer is above the base epitaxial layer and above a bottommost channel layer; and
forming an epitaxial feature in the source/drain recess, wherein the epitaxial feature is above the insulation layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the insulation layer separates the base epitaxial layer from contacting the epitaxial feature.

### Claim 3 (depends on 1)

The method of claim 1, wherein the insulation layer fully covers sidewalls of the bottommost channel layer.

### Claim 4 (depends on 3)

The method of claim 3, wherein a top surface of the base epitaxial layer is below a bottom surface of the bottommost channel layer and above a top surface of a bottommost sacrificial layer.

### Claim 5 (depends on 1)

The method of claim 1, wherein the base epitaxial layer fully covers sidewalls of the bottommost channel layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein the insulation layer and the base epitaxial layer collectively cover sidewalls of the bottommost channel layer.

### Claim 7 (depends on 1)

The method of claim 1, wherein the depositing of the insulation layer includes a cyclic deposition process.

### Claim 8 (depends on 1)

The method of claim 1, wherein the depositing of the insulation layer includes a plasma-enhanced chemical vapor deposition (PECVD) process.

### Claim 9 (depends on 1)

The method of claim 1, further comprising:
forming first and second dielectric fins sandwiching the semiconductor fin, wherein the depositing of the insulation layer traps first air gaps under the insulation layer at corner regions of the first and second dielectric fins.

### Claim 10 (depends on 9)

The method of claim 9, wherein the forming of the epitaxial feature traps second air gaps between the epitaxial feature and the insulation layer, and the second air gaps are above the first air gaps.

### Claim 11

A method of fabricating a semiconductor device, comprising:
forming an epitaxial stack of channel layers and sacrificial layers on a semiconductor substrate, the channel layers and the sacrificial layers having different material compositions and being alternatingly stacked in a vertical direction;
patterning the epitaxial stack to form a first semiconductor fin in a first region of the semiconductor substrate and a second semiconductor fin in a second region of the semiconductor substrate;
recessing the first semiconductor fin in a first source/drain region;
recessing the second semiconductor fin in a second source/drain region;
forming an epitaxial layer in the first and second source/drain regions;
forming a dielectric layer on the epitaxial layer in the first and second source/drain regions, wherein a top surface of the dielectric layer in the first source/drain region is above the top surface of the dielectric layer in the second source/drain region; and
forming a first source/drain feature in the first source/drain region and a second source/drain feature in the second source/drain region, wherein the second source/drain feature is in contact with a bottommost channel layer in the second semiconductor fin, and the first source/drain feature is free of contact with a bottommost channel layer in the first semiconductor fin.

### Claim 12 (depends on 11)

The method of claim 11, wherein the first source/drain feature is free of contact with two or more bottom channel layers in the first semiconductor fin.

### Claim 13 (depends on 11)

The method of claim 11, wherein the forming of epitaxial layer includes:
growing the epitaxial layer in the first and second source/drain regions;
depositing a masking layer covering the epitaxial layer in the second source/drain region;
continue growing the epitaxial layer in the first source/drain region; and
removing the masking layer.

### Claim 14 (depends on 11)

The method of claim 11, wherein the forming of the dielectric layer includes:
depositing the dielectric layer, such that the top surface of the dielectric layer in the first source/drain region is above the bottommost channel layer in the first semiconductor fin, and the top surface of the dielectric layer in the second source/drain region is above the bottommost channel layer in the second semiconductor fin;
depositing a masking layer covering the dielectric layer in the first source/drain region;
recessing the top surface of the dielectric layer in the second source/drain region; and
removing the masking layer.

### Claim 15 (depends on 11)

The method of claim 11, further comprising:
removing the sacrificial layers from the first and second semiconductor fins; and
forming a gate structure, wherein the gate structure wraps around each of the channel layers in the first and second semiconductor fins.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
forming inner spacers abutting the gate structure, wherein at least a bottommost inner spacer is laterally stacked between the dielectric layer and the gate structure.

### Claim 17

A method, comprising:
forming a stack of channel layers and sacrificial layers on a substrate, the channel layers and the sacrificial layers having different material compositions and being alternatingly disposed in a vertical direction;
patterning the stack to form a fin-shaped structure;
recessing a region the fin-shaped structure to form a trench;
depositing inner spacers in the trench and on sidewalls of the sacrificial layers;
depositing a first epitaxial layer in the trench, wherein a top surface of the base epitaxial layer is below a top surface of a bottommost one of the channel layers;
depositing an insulation layer in the trench and on the first epitaxial layer, wherein a top surface of the insulation layer is above the top surface of the bottommost one of the channel layers; and
forming a second epitaxial layer in the trench and on the insulating layer, wherein the second epitaxial layer abuts at least a topmost one of the channel layers.

### Claim 18 (depends on 17)

The method of claim 17, wherein the first epitaxial layer is in contact with a bottommost one of the inner spacers.

### Claim 19 (depends on 17)

The method of claim 17, wherein the insulation layer separates the first epitaxial layer from contacting the second epitaxial layer.

### Claim 20 (depends on 17)

The method of claim 17, further comprising:
depositing an isolation feature on sidewalls of the fin-shaped structure, wherein a bottom surface of the first epitaxial layer is below a top surface of the isolation feature.