# US 12,191,369 B2 · Source and drain engineering process for multigate devices

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- Number: US 12,191,369 B2
- Document ID: US12191369B2
- Status: Granted
- Kind: B2
- Application number: 17/464,265
- Filed: 2021-09-01
- Published: 2022-10-06
- Granted: 2025-01-07
- Earliest claimed: 2021-03-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Po-Yu Lin; Wei-Yang Lee; Chia-Pin Lin; Tzu-Hua Chiu; Kuan-Hao Cheng; Wei-Han Fan; Yee-Chia Yeo; Wei Hao Lu
- Web page: https://patentgrep.com/patent/US12191369B2

## CPC

- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes a first semiconductor layers and a second semiconductor layers alternatively disposed, the first semiconductor layers and the second semiconductor layers being different in composition; patterning the semiconductor stack to form a semiconductor fin; forming a dielectric fin next to the semiconductor fin; forming a first gate stack on the semiconductor fin and the dielectric fin; etching to a portion of the semiconductor fin within a source/drain region, resulting in a source/drain recess; and epitaxially growing a source/drain feature in the source/drain recess, defining an airgap spanning between a sidewall of the source/drain feature and a sidewall of the dielectric fin.

## Claims

### Claim 1

A method, comprising:
forming a semiconductor stack on a substrate, wherein the semiconductor stack includes a first semiconductor layers and a second semiconductor layers alternatively disposed, the first semiconductor layers and the second semiconductor layers being different in composition;
patterning the semiconductor stack to form a semiconductor fin;
forming an isolation feature over the substrate to surround a bottom portion of the semiconductor fin;
after the forming of the isolation feature, depositing a cladding layer along a top surface and sidewalls of the semiconductor fin;
after the depositing of the cladding layer, forming a dielectric fin over a top surface of the isolation feature next to the semiconductor fin;
forming a first gate stack on the semiconductor fin and the dielectric fin;
after the forming of the first gate stack, selectively removing the cladding layer;
etching to a portion of the semiconductor fin within a source/drain region, resulting in a source/drain recess; and
epitaxially growing a source/drain feature in the source/drain recess, defining an airgap spanning between a sidewall of the source/drain feature and a sidewall of the dielectric fin.

### Claim 2 (depends on 1)

The method of claim 1, further comprising depositing a dielectric layer to seal the airgap.

### Claim 3 (depends on 2)

The method of claim 2, wherein the dielectric layer includes at least one of a contact etch-stop layer and an inter-layer dielectric layer.

### Claim 4 (depends on 2)

The method of claim 2, wherein
the semiconductor fin and the dielectric fin longitudinally extend along a first direction, and being spaced away along a second direction that is orthogonal to the first direction;
the first gate stack longitudinally extends along the second direction; and
the source/drain feature is formed on the semiconductor fin with the airgap spanning between the source/drain feature and the dielectric fin along the second direction.

### Claim 5 (depends on 4)

The method of claim 4, further comprising
a second gate stack longitudinally extends along the second direction and is spaced away from the first gate stack along the first direction; and
a first gate spacer disposed on a sidewall of the first gate stack and a second gate spacer disposed on a sidewall of the second gate stack, wherein the airgap spans between the first gate spacer and the second gate spacer along the first direction.

### Claim 6 (depends on 4)

The method of claim 4, wherein
the semiconductor fin extends above the top surface of the isolation feature; and
the airgap vertically spans from the dielectric layer to the isolation feature.

### Claim 7 (depends on 2)

The method of claim 2, wherein the epitaxially growing a source/drain feature includes epitaxially growing the source/drain feature using a precursor having a deposition chemical and an etching chemical.

### Claim 8 (depends on 7)

The method of claim 7, wherein
the deposition chemical includes at least one of SiH4, GeH4 and SiH2Cl2; and
the etching chemical includes at least one of HCl, Cl2 and SF6.

### Claim 9 (depends on 8)

The method of claim 8, wherein the epitaxially growing a source/drain feature includes applying HCl with a flowrate of HCl less than 20000 sccm, resulting in the source/drain feature with a lollipop-like shape.

### Claim 10 (depends on 8)

The method of claim 8, wherein the epitaxially growing a source/drain feature includes applying HCl with a flowrate of HCl greater than 40000 sccm, resulting in the source/drain feature with a bar-like shape.

### Claim 11 (depends on 2)

The method of claim 2, wherein the epitaxially growing a source/drain feature includes epitaxially growing the source/drain feature in a cyclic process, wherein each cycle includes a first duration of deposition using a first precursor having a deposition chemical and a second duration of etching using a second precursor having an etching chemical.

### Claim 12 (depends on 11)

The method of claim 11, wherein a ratio of the first duration over the second duration is greater than 0.5, resulting in the source/drain feature with a lollipop-like shape.

### Claim 13 (depends on 11)

The method of claim 11, wherein a ratio of the first duration over the second duration is less than 0.5, resulting in the source/drain feature with a bar-like shape.

### Claim 14 (depends on 1)

The method of claim 1, further comprising:
removing the first gate stack, resulting in a gate trench in an inter-layer dielectric (ILD) layer;
selectively removing the first semiconductor layers within the gate trench; and
depositing a gate dielectric layer and a gate conductive layer surrounding each of the second semiconductor layers, wherein the source/drain feature contacts each of the second semiconductor layers.

### Claim 15

A method, comprising:
forming a semiconductor stack on a substrate, wherein the semiconductor stack includes a first semiconductor layers and a second semiconductor layers alternatively disposed, the first semiconductor layers and the second semiconductor layers being different in composition;
patterning the semiconductor stack to form a semiconductor fin;
forming an isolation feature over the substrate to surround a bottom portion of the semiconductor fin;
after the forming of the isolation feature, depositing a semiconductor cladding layer along a top surface and sidewalls of the semiconductor fin;
after the depositing of the semiconductor cladding layer, forming a dielectric fin over a top surface of the isolation feature next to the semiconductor fin;
forming a first gate stack on the semiconductor fin and the dielectric fin;
after the forming of the first gate stack, selectively removing the semiconductor cladding layer;
etching to a portion of the semiconductor fin within a source/drain region, resulting in a source/drain recess; and
epitaxially growing a source/drain feature in the source/drain recess in a cyclic process, defining an airgap spanning between a sidewall of the source/drain feature and a sidewall of the dielectric fin, wherein each cycle of the cyclic process includes a first duration of deposition using a first precursor having a deposition chemical and a second duration of etching using a second precursor having an etching chemical.

### Claim 16 (depends on 15)

The method of claim 15, wherein
the deposition chemical includes at least one of SiH4, GeH4 and SiH2Cl2; and
the etching chemical includes at least one of HCl, Cl2 and SF6.

### Claim 17 (depends on 15)

The method of claim 15, wherein a ratio of the first duration over the second duration is greater than 0.5, resulting in the source/drain feature with a lollipop-like shape.

### Claim 18

A method, comprising:
forming a semiconductor stack on a substrate, wherein the semiconductor stack includes a first semiconductor layers and a second semiconductor layers alternatively disposed, the first semiconductor layers and the second semiconductor layers being different in composition;
patterning the semiconductor stack to form a semiconductor fin;
forming an isolation feature over the substrate to surround a bottom portion of the semiconductor fin;
after the forming of the isolation feature, depositing a semiconductor cladding layer along a top surface and sidewalls of the semiconductor fin;
after the depositing of the semiconductor cladding layer, forming a dielectric fin over a top surface of the isolation feature next to the semiconductor fin;
forming a first gate stack on the semiconductor fin and the dielectric fin;
after the forming of the first gate stack, selectively removing the semiconductor cladding layer;
etching to a portion of the semiconductor fin within a source/drain region, resulting in a source/drain recess; and
epitaxially growing a source/drain feature in the source/drain recess in a cyclic process, defining an airgap spanning between a sidewall of the source/drain feature and a sidewall of the dielectric fin, wherein each cycle of the cyclic process includes a first duration of deposition using a first precursor having a silicon-containing deposition chemical and a second duration of etching using a second precursor having a chlorine-containing etching chemical.

### Claim 19 (depends on 18)

The method of claim 18, wherein
the silicon-containing deposition chemical includes SiH2Cl2; and
the chlorine-containing etching chemical includes HCl.

### Claim 20 (depends on 18)

The method of claim 18, wherein the epitaxially growing a source/drain feature includes applying HCl with a flowrate of HCl less than 20000 sccm, resulting in the source/drain feature with a lollipop-like shape.