# US 12,191,368 B2 · Semiconductor device

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- Number: US 12,191,368 B2
- Document ID: US12191368B2
- Status: Granted
- Kind: B2
- Application number: 17/455,681
- Filed: 2021-11-19
- Published: 2022-09-08
- Granted: 2025-01-07
- Earliest claimed: 2021-03-02
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Yonghee Park; Munhyeon Kim; Uihui Kwon; Joohyung You; Daewon Ha
- Web page: https://patentgrep.com/patent/US12191368B2

## CPC

- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/0195: {forming inner spacers between adjacent channels, e.g. changing their shapes or sizes}
- H10D 30/508: {characterised by the relative sizes, shapes or dispositions of the inner spacers}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/60: Impurity distributions or concentrations
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 62/364: {of IGFETs}
- H10D 84/0128: {Manufacturing their channels}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device includes active regions extending on a substrate in a first direction, gate structures intersecting the active regions and extending on the substrate in a second direction, source/drain regions in recess regions in which the active regions are recessed, on both sides of each of the gate structures, and contact plugs connected to the source/drain regions, wherein each of the source/drain regions include first and second epitaxial layers sequentially stacked on the active regions in the recess regions in a third direction perpendicular to an upper surface of the substrate, respectively, and wherein ratios of the first epitaxial layer thickness in the third direction to the second epitaxial layer thickness in the third direction are different in different ones of the source/drain regions.

## Claims

### Claim 1

A semiconductor device comprising:
active regions extending on a substrate in a first direction;
first and second gate structures intersecting the active regions and extending on the substrate in a second direction;
a plurality of channel layers spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, on the active regions and surrounded in the second and third directions by the first and second gate structures;
first and second source/drain regions in recess regions in which the active regions are recessed on at least one side of each of the first and second gate structures, and physically contacting the plurality of channel layers; and
contact plugs connected to the first and second source/drain regions,
wherein each of the first and second source/drain regions includes:
a first epitaxial layer on each of the active regions in each of the recess regions; and
a second epitaxial layer on the first epitaxial layer and including first conductivity-type impurities,
the first epitaxial layer has a maximum first thickness in the third direction in the first source/drain region, and
the first epitaxial layer has a maximum second thickness less than the maximum first thickness in the third direction in the second source/drain region.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the second epitaxial layer has a first depth in the third direction in the first source/drain region, and the second epitaxial layer has a second depth deeper than the first depth in the third direction in the second source/drain region.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first and second source/drain regions have substantially a same thickness.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the first and second source/drain regions have upper ends and lower ends respectively positioned at substantially a same height level in the third direction.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein a number of the channel layers connected to the second epitaxial layer, among the plurality of channel layers, in the first source/drain region is less than a number of the channel layers connected to the second epitaxial layer, among the plurality of channel layers, in the second source/drain region.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the first epitaxial layer includes a semiconductor material.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the first epitaxial layer includes second conductivity-type impurities.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the first epitaxial layer includes the second conductivity-type impurities at a first concentration, and the second epitaxial layer includes the first conductivity-type impurities at a second concentration higher than the first concentration.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the first epitaxial layer includes at least one of silicon oxide, silicon nitride, or silicon oxynitride.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the first epitaxial layer is a single crystal.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein the second epitaxial layer is on side surfaces of at least some of the plurality of channel layers.

### Claim 12 (depends on 1)

The semiconductor device of claim 1, wherein the first gate structure constitutes a part of transistors connected in parallel, and
wherein the second gate structure constitutes a part of transistors connected in series.

### Claim 13 (depends on 1)

The semiconductor device of claim 1, wherein the contact plugs are each connected to the second epitaxial layer.

### Claim 14 (depends on 1)

The semiconductor device of claim 1, further comprising internal spacer layers between the first and second gate structures and the first and second source/drain regions in the first direction.

### Claim 15

A semiconductor device comprising:
active regions extending on a substrate in a first direction;
gate structures intersecting the active regions and extending on the substrate in a second direction;
source/drain regions in recess regions in which the active regions are recessed, on both sides of each of the gate structures; and
contact plugs connected to the source/drain regions,
wherein each of the source/drain regions includes first and second epitaxial layers sequentially stacked on the active regions in the recess regions in a third direction perpendicular to an upper surface of the substrate, respectively, and
wherein ratios of the first epitaxial layer thickness in the third direction to the second epitaxial layer thickness in the third direction are different in different ones of the source/drain regions.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the second epitaxial layer is doped with first conductivity type impurities, and the first epitaxial layer is not doped with the first conductivity type impurities.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein the first epitaxial layer is doped with second conductivity type impurities.

### Claim 18 (depends on 16)

The semiconductor device of claim 16, wherein the first epitaxial layer is an insulating layer.

### Claim 19

A semiconductor device comprising:
active regions extending on a substrate in a first direction;
gate structures intersecting the active regions and extending on the substrate in a second direction;
a plurality of channel layers spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, on the active regions and surrounded in the second and third directions by the gate structures; and
source/drain regions in recess regions in which the active regions are recessed on at least one side of each of the gate structures,
wherein each of the source/drain regions includes first and second epitaxial layers sequentially stacked on the active regions in the recess regions in the third direction, respectively,
wherein the source/drain regions include a first source/drain region in which the second epitaxial layer is at a maximum first depth and a second source/drain region in which the second epitaxial layer is at a maximum second depth different from the maximum first depth, and
wherein the sums of thicknesses of the first and second epitaxial layers in the third direction in the first and second source/drain regions are substantially equal.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein the second epitaxial layer includes a first conductivity-type semiconductor, and the first epitaxial layer includes a second conductivity-type semiconductor.