# US 12,191,367 B2 · Multi-finger transistor structure and method of manufacturing the same

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- Number: US 12,191,367 B2
- Document ID: US12191367B2
- Status: Granted
- Kind: B2
- Application number: 17/752,888
- Filed: 2022-05-25
- Published: 2023-05-25
- Granted: 2025-01-07
- Earliest claimed: 2021-11-19
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Su Xing; Purakh Raj Verma; Rudy Octavius Sihombing; Shyam Parthasarathy; Jinyu Liao
- Web page: https://patentgrep.com/patent/US12191367B2

## CPC

- H10D 30/6744: {Monocrystalline silicon}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/6717: {the source and the drain regions being asymmetrical}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A multi-finger transistor structure is provided in the present invention, including multiple active areas, a gate structure consisting of multiple gate parts and connecting parts, wherein each gate part crosses over one of the active areas and each connecting part alternatively connects one end and the other end of the gate parts so as to form a meander gate structure, and multiple sources and drains, wherein one source and one drain are set between two adjacent gate parts, and each gate parts is accompanied by one source and one drain at two sides respectively, and the distance between the drain and the gate part is larger than the distance between the source and the gate part, so that the source and the drain are asymmetric with respect to the corresponding gate part, and air gaps are formed in the dielectric layer between each drain and the corresponding gate part.

## Claims

### Claim 1

A multi-finger transistor structure, comprising:
multiple active areas;
a gate structure, comprising multiple gate parts and multiple connecting parts, wherein each said gate part traverses one of said active areas, and each connecting part alternatively connect one end and the other end of two adjacent said gate parts, so as to form meander said gate structure;
multiple sources and drains, wherein one of said sources and one of said drains are set between two adjacent said gate parts, and one of said sources and one of said drains are set at two sides of each said gate part, and a distance between said drain and corresponding said gate part is larger than a distance between said source and corresponding said gate part; and
air gaps in a dielectric layer between each said drain and corresponding said gate part.

### Claim 2 (depends on 1)

The multi-finger transistor structure of claim 1, further comprising multiple contacts on each said drains and each said source, wherein a distance between said contacts on said drain and corresponding said gate part is larger than a distance between said contacts on said source and corresponding said gate part, so that said contacts on said source and said contacts on corresponding said drain are asymmetric with respect to corresponding said gate part.

### Claim 3 (depends on 2)

The multi-finger transistor structure of claim 2, wherein said contacts on each said source connect to one corresponding first metal layer, and said contacts on each said drain connect to another corresponding first metal layer.

### Claim 4 (depends on 1)

The multi-finger transistor structure of claim 1, further comprising multiple contacts on each said connecting part.

### Claim 5 (depends on 1)

The multi-finger transistor structure of claim 1, wherein said air gaps are further between adjacent said drain and said source.

### Claim 6 (depends on 1)

The multi-finger transistor structure of claim 1, wherein multiple said air gaps are formed in said dielectric layer between each said drain and corresponding said gate part.

### Claim 7 (depends on 1)

The multi-finger transistor structure of claim 1, wherein said dielectric layer comprises an interlayer dielectric layer, a first inter-metal layer and a second inter-metal layer.

### Claim 8 (depends on 1)

The multi-finger transistor structure of claim 1, wherein said gate structure connects to a radio frequency input, and said source connects to a ground, and said drain connects to a radio frequency output.

### Claim 9 (depends on 1)

The multi-finger transistor structure of claim 1, wherein a shallow trench isolation is formed between adjacent said active areas to isolate therebetween.