# US 12,191,362 B2 · Stacked semiconductor devices in sealants and interconnected with pillar electrodes

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- Number: US 12,191,362 B2
- Document ID: US12191362B2
- Status: Granted
- Kind: B2
- Application number: 17/690,788
- Filed: 2022-03-09
- Published: 2022-09-15
- Granted: 2025-01-07
- Earliest claimed: 2021-03-11
- Assignees: AOI Electronics Co., Ltd.
- Applicants: AOI Electronics Co., Ltd.
- Inventors: Takashi Suzuki
- Web page: https://patentgrep.com/patent/US12191362B2

## CPC

- H10D 64/20: Electrodes characterised by their shapes, relative sizes or dispositions
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10D 64/01: Manufacture or treatment
- H10D 64/66: Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 72/0198: {batch processes}
- H10W 90/00: Package configurations
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/9413: {on encapsulations}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Problem: To reduce the likelihood of insufficient electrical continuity in wiring in a semiconductor device. Solution: A method for manufacturing a semiconductor device includes placing, on a substrate surface, a first semiconductor element having a first surface on which a first pillar electrode is formed, via a surface opposite to the first surface, sealing a substrate-side pillar electrode and the first pillar electrode with a first sealant, removing a part of the first sealant to expose an end of the substrate-side pillar electrode and an end of the first pillar electrode, forming, on the first sealant, a plating layer electrically connected to the substrate-side pillar electrode and the first pillar electrode by plating, removing a part of the plating layer to form a residual plating layer, coupling a second semiconductor element onto the residual plating layer or a metal layer or a wiring layer formed on the residual plating layer, and sealing the residual plating layer and the second semiconductor element using a second sealant such that the first sealant is in contact with the second sealant.

## Claims

### Claim 1

A semiconductor device comprising:
a first semiconductor element having a first surface provided with a first pillar electrode; and a second semiconductor element having a second surface provided with a plurality of second pillar electrodes, the semiconductor device further comprising:
a connecting layer electrically connecting a second pillar electrode formed in a first portion of the second surface to the first pillar electrode, the first portion facing the first surface;
a third pillar electrode electrically connecting a second pillar electrode formed in a second portion of the second surface to an outside of the semiconductor device, the second portion being different from the first portion;
a first sealant sealing the first pillar electrode and the third pillar electrode; and
a second sealant in contact with the first sealant, the second sealant sealing the plurality of second pillar electrodes,
wherein an end face of the first pillar electrode, an end face of the third pillar electrode and an end face of the first sealant are on a same plane, and
the connecting layer is formed on the same plane.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein
the connecting layer in contact with the first pillar electrode has a cross section parallel to the first surface, an area of the cross section being larger than an area of a surface of the first pillar electrode in contact with the connecting layer.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein
an area of a cross section of the third pillar electrode parallel to the second surface is smallest at a position other than both ends of the third pillar electrode.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein
no insulating layer is provided between the first sealant and the second sealant.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein
a length along a conductive portion electrically connecting a bottom portion of the first pillar electrode to a terminal of the second semiconductor element is 100 μm or less.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein
a length along a conductive portion electrically connecting an upper portion of the second pillar electrodes to a surface of an external connection terminal is 500 μm or less.