# US 12,191,361 B2 · Transistor structure with multi-layer field plate and related method

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,191,361 B2
- Document ID: US12191361B2
- Status: Granted
- Kind: B2
- Application number: 17/656,277
- Filed: 2022-03-24
- Published: 2023-09-28
- Granted: 2025-01-07
- Earliest claimed: 2022-03-24
- Assignees: GlobalFoundries U.S. Inc.
- Applicants: GlobalFoundries U.S. Inc.
- Inventors: Ketankumar Harishbhai Tailor
- Web page: https://patentgrep.com/patent/US12191361B2

## CPC

- H10D 64/112: {comprising multiple field plate segments}
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/0278: {forming single crystalline channels on wafers after forming insulating device isolations}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate}
- H10D 30/751: {having composition variations in the channel regions}
- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 64/111: {Field plates}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0144: {Manufacturing their gate insulating layers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A transistor structure with a multi-layer field plate and related methods are disclosed. The transistor structure includes a dielectric layer that has a thinner portion over a first doped well and a second doped well, and a thicker portion adjacent the thinner portion and over the second doped well. The thicker portion has a height greater than the thinner portion above the doped wells. The transistor includes a first gate structure on the thinner portion and a field plate on the thicker portion of the dielectric layer.

## Claims

### Claim 1

A transistor structure, comprising:
a field plate over a first dielectric layer, the field plate including:
a first layer including a high dielectric constant metal gate (HKMG) stack, the HKMG stack including a work function metal (WFM) embedded within a high dielectric constant (high-K) material and a metal layer over an upper surface of the high-K material, and
a second layer over the first layer; and
a gate structure over the first dielectric layer and laterally adjacent to the field plate, the gate structure including:
a polysilicon layer, and
a gate spacer laterally between the polysilicon layer and the field plate.

### Claim 2 (depends on 1)

The transistor structure of claim 1, wherein the gate structure does not include the HKMG stack, and wherein the second layer of the field plate includes polysilicon or amorphous silicon.

### Claim 3 (depends on 1)

The transistor structure of claim 1, wherein the first dielectric layer further includes:
a first portion over a doped well region including a first doped well and a second doped well, the first portion having a first height above the doped well region, and
a second portion adjacent the first portion and over the second doped well, the second portion having a second height above the second doped well region greater than the first height,
wherein the gate structure is over the first portion and the second portion, and the field plate is over the second portion.

### Claim 4 (depends on 3)

The transistor structure of claim 3, wherein the gate structure further includes:
a second dielectric layer vertically between the polysilicon layer and the first dielectric layer,
wherein the gate spacer laterally separates the second dielectric layer and the field plate.

### Claim 5 (depends on 1)

The transistor structure of claim 1, wherein the field plate is laterally distal to a complementary metal oxide semiconductor (CMOS) device and laterally distal to a flash memory cell structure.

### Claim 6

A transistor structure, comprising:
a field plate over a first dielectric layer, the field plate including:
a first layer including a high dielectric constant metal gate (HKMG) stack, and
a second layer over the first layer,
a hard mask remnant vertically between the first layer and the first dielectric layer; and
a gate structure over the first dielectric layer and laterally adjacent to the field plate, the gate structure including:
a polysilicon layer, and
a gate spacer laterally between the polysilicon layer and the field plate.

### Claim 7 (depends on 6)

The transistor structure of claim 6, wherein the HKMG stack includes a work function metal (WFM) embedded within a high dielectric constant (high-K) material and a metal layer over an upper surface of the high-K material.

### Claim 8 (depends on 6)

The transistor structure of claim 6, wherein the gate structure does not include the HKMG stack, and wherein the second layer of the field plate includes polysilicon or amorphous silicon.

### Claim 9 (depends on 6)

The transistor structure of claim 6, wherein the first dielectric layer further includes:
a first portion over a doped well region including a first doped well and a second doped well, the first portion having a first height above the doped well region, and
a second portion adjacent the first portion and over the second doped well, the second portion having a second height above the second doped well region greater than the first height,
wherein the gate structure is over the first portion and the second portion, and the field plate is over the second portion.

### Claim 10 (depends on 9)

The transistor structure of claim 9, wherein the gate structure further includes:
a second dielectric layer vertically between the polysilicon layer and the first dielectric layer,
wherein the gate spacer laterally separates the second dielectric layer and the field plate.

### Claim 11 (depends on 6)

The transistor structure of claim 6, wherein the field plate is laterally distal to a complementary metal oxide semiconductor (CMOS) device and laterally distal to a flash memory cell structure.

### Claim 12 (depends on 11)

The transistor IC structure of claim 11, wherein the flash memory cell structure includes:
a pair of word line gate structures including a first word line gate structure and a second word line gate structure, the pair of word line gate structures having a first height above a substrate;
a pair of control gate structures including a first control gate structure and a second control gate structure, the pair of control gate structures laterally between the pair of word line gate structures and having a second height above the substrate less than the first height;
a pair of gate spacers including a first gate spacer and a second gate spacer, the first gate spacer laterally between the first control gate structure and the first word line gate structure, and the second gate spacer laterally between the second control gate structure and second word line gate structure; and
an erase gate structure laterally between the pair of control gate structures,
wherein the field plate has a third height above the substrate greater than the first height.

### Claim 13 (depends on 12)

The transistor IC structure of claim 12, wherein each of the pair of word line gate structures includes:
a first layer including the HKMG stack, and
a second layer over the first layer, the second layer including polysilicon.

### Claim 14 (depends on 12)

The transistor structure of claim 12, wherein the pair of gate spacers of the flash memory cell structure and the gate spacer of the gate structure each includes a horizontally tapered end.

### Claim 15

A method of forming a transistor structure, comprising:
forming a field plate over a first dielectric layer, the field plate including:
a first layer including a high dielectric constant metal gate (HKMG) stack, the HKMG stack having a work function metal (WFM) embedded within a high dielectric constant (high-K) material and a metal layer over an upper surface of the high-K material, and
a second layer over the first layer; and
forming a gate structure over the first dielectric layer and laterally adjacent to the field plate, the gate structure including:
a polysilicon layer, and
a gate spacer laterally between the polysilicon layer and the field plate.

### Claim 16 (depends on 15)

The method of claim 15, wherein the second layer of the field plate includes polysilicon or amorphous silicon, and wherein the gate structure does not include the HKMG stack.

### Claim 17 (depends on 15)

The method of claim 15, wherein forming the field plate over the first dielectric layer includes:
forming a first portion of the first dielectric layer over a doped well region including a first doped well and a second doped well, the first portion having a first height above the doped well region, and
forming a second portion of the first dielectric layer adjacent the first portion and over the second doped well, the second portion having a second height above the second doped well region greater than the first height.

### Claim 18 (depends on 17)

The method of claim 17, wherein forming the field plate includes forming a hard mask remnant vertically between the first layer of the field plate and the second portion of the first dielectric layer.

### Claim 19 (depends on 17)

The method of claim 17, wherein forming the gate structure includes forming a second dielectric layer vertically between the polysilicon layer and the first dielectric layer.

### Claim 20 (depends on 15)

The method of claim 15, further comprising:
forming a wordline gate structure within a flash memory cell structure simultaneously with the field plate; and
forming a gate structure of a complementary metal oxide semiconductor (CMOS) device simultaneously with the field plate,
wherein the field plate is laterally distal to the CMOS device and the wordline gate structure.