# US 12,191,354 B2 · Vertical transistors having at least 50% grain boundaries offset between top and bottom source/drain regions and the channel region that is vertically therebetween

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- Number: US 12,191,354 B2
- Document ID: US12191354B2
- Status: Granted
- Kind: B2
- Application number: 17/860,325
- Filed: 2022-07-08
- Published: 2022-10-27
- Granted: 2025-01-07
- Earliest claimed: 2019-08-09
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Manuj Nahar; Vassil N. Antonov; Kamal M. Karda; Michael Mutch; Hung-Wei Liu; Jeffery B. Hull
- Web page: https://patentgrep.com/patent/US12191354B2

## CPC

- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/6728: {Vertical TFTs}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/124: {Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions}
- H10D 62/40: Crystalline structures
- H10P 14/3456: {Polycrystalline}
- H10P 14/3816: {Pulsed laser beam}
- H10P 14/3211: {Silicon, silicon germanium or germanium}
- H10P 14/3248: {consisting of two layers}
- H10P 14/3256: {Microstructure}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. The channel region is crystalline and comprises a plurality of vertically-elongated crystal grains that individually are directly against both of the top source/drain region and the bottom source/drain region. Other embodiments, including methods, are disclosed.

## Claims

### Claim 1

A vertical transistor comprising:
a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region;
the top and bottom source/drain regions having polycrystalline crystal grains and grain boundaries between immediately-adjacent of the polycrystalline crystal grains; the channel region having channel crystal grains having a first average crystal grain size and comprising grain boundaries between immediately-adjacent of the channel crystal grains, the top source/drain region having a second average crystal grain size, and the bottom source/drain region having a third average crystal grain size that differs from the second average crystal grain size;
the top source/drain region and the channel region having a top interface and the bottom source/drain region and the channel region having a bottom interface;
at least 50% of the grain boundaries in the top source/drain region at the top interface being laterally offset from the grain boundaries of the channel crystal grains in the channel region at the top interface; and
at least 50% of the grain boundaries in the bottom source/drain region at the bottom interface being laterally offset from the grain boundaries of the channel crystal grains in the channel region at the bottom interface.

### Claim 2 (depends on 1)

The vertical transistor of claim 1 wherein,
at least 75% of the grain boundaries in the top source/drain region at the top interface are laterally offset from the grain boundaries of the channel crystal grains in the channel region at the top interface; and
at least 75% of the grain boundaries in the bottom source/drain region at the bottom interface are laterally offset from the grain boundaries of the channel crystal grains in the channel region at the bottom interface.

### Claim 3 (depends on 2)

The vertical transistor of claim 2 wherein,
at least 85% of the grain boundaries in the top source/drain region at the top interface are laterally offset from the grain boundaries of the channel crystal grains in the channel region at the top interface; and
at least 85% of the grain boundaries in the bottom source/drain region at the bottom interface are laterally offset from the grain boundaries of the channel crystal grains in the channel region at the bottom interface.

### Claim 4 (depends on 1)

The vertical transistor of claim 1 wherein the first average crystal grain size differs relative to both the second average crystal grain size and the third average crystal grain size.

### Claim 5 (depends on 1)

The vertical transistor of claim 1 wherein the first average crystal grain size differs relative to only one of the second average crystal grain size and the third average crystal grain size.

### Claim 6

A vertical transistor comprising:
a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region;
the top and bottom source/drain regions having polycrystalline crystal grains and grain boundaries between immediately-adjacent of the polycrystalline crystal grains; the channel region having channel crystal grains comprising grain boundaries between immediately-adjacent of the channel crystal grains;
the top source/drain region and the channel region having a top interface and the bottom source/drain region and the channel region having a bottom interface;
at least 50% of the grain boundaries in the top source/drain region at the top interface being laterally offset from the grain boundaries of the channel crystal grains in the channel region at the top interface; and
at least 50% of the grain boundaries in the bottom source/drain region at the bottom interface being laterally offset from the grain boundaries of the channel crystal grains in the channel region at the bottom interface; wherein a plurality of the channel grain boundaries are vertically-elongated crystal grains that individually are directly against both of the top source/drain region and the bottom source/drain region.

### Claim 7

A vertical transistor comprising:
a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region;
the top and bottom source/drain regions having polycrystalline crystal grains and grain boundaries between immediately-adjacent of the polycrystalline crystal grains; the channel region having channel crystal grains comprising grain boundaries between immediately-adjacent of the channel crystal grains;
the top source/drain region and the channel region having a top interface and the bottom source/drain region and the channel region having a bottom interface;
at least 50% of the grain boundaries in the top source/drain region at the top interface being laterally offset from the grain boundaries of the channel crystal grains in the channel region at the top interface; and
at least 50% of the grain boundaries in the bottom source/drain region at the bottom interface being laterally offset from the grain boundaries of the channel crystal grains in the channel region at the bottom interface; wherein,
one and only one of the grain boundaries in the top source/drain region at the top interface being laterally aligned with one and only one of the grain boundaries of the channel crystal grains in the channel region at the top interface; and
one and only one of the grain boundaries in the bottom source/drain region at the bottom interface being laterally aligned with one and only one of the grain boundaries of the channel crystal grains in the channel region at the bottom interface.