# US 12,191,352 B2 · Using different work-functions to reduce gate-induced drain leakage current in stacked nanosheet transistors

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- Number: US 12,191,352 B2
- Document ID: US12191352B2
- Status: Granted
- Kind: B2
- Application number: 17/483,870
- Filed: 2021-09-24
- Published: 2023-03-30
- Granted: 2025-01-07
- Earliest claimed: 2021-09-24
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Takashi Ando; Ruilong Xie; Pouya Hashemi; Alexander Reznicek
- Web page: https://patentgrep.com/patent/US12191352B2

## CPC

- H10D 62/121: {oriented parallel to substrates}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 30/0193: {by modifying properties of the stacked channels}
- H10D 30/502: {characterised by the stacked channels}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 64/01: Manufacture or treatment
- H10D 64/514: {characterised by the insulating layers}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10D 84/834: {comprising FinFETs}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Embodiments of the invention are directed to a transistor device that includes a channel stack having stacked, spaced-apart, channel layers. A first source or drain (S/D) region is communicatively coupled to the channel stack. A tunnel extends through the channel stack, wherein the tunnel includes a central region and a first set of end regions. The first set of end regions is positioned closer to the first S/D region than the central region is to the first S/D region. A first type of work-function metal (WFM) is formed in the first set of end regions, the first WFM having a first work-function (WF). A second type of WFM is formed in the central region, the second type of WFM having a second WF, wherein the first WF is different than the second WF.

## Claims

### Claim 1

An integrated circuit (IC) having transistor devices comprising a first transistor type, the first transistor type comprising:
a channel stack comprising first stacked, spaced-apart, channel layers;
wherein a first one of the first stacked, spaced-apart channel layers comprises a first trimmed channel region and first non-trimmed channel regions;
a first source or drain (S/D) region communicatively coupled to the channel stack;
a tunnel extending through the channel stack;
wherein a first portion of a boundary of the tunnel is defined by the first trimmed channel region;
wherein the tunnel comprises a central region and a first set of end regions;
wherein the first set of end regions is closer to the first S/D region than the central region is to the first S/D region;
a first type of work-function metal (WFM) formed in the first set of end regions, the first WFM having a first work-function (WF); and
a second type of WFM formed in the central region, the second type of WFM having a second WF;
wherein the first WF is different than the second WF.

### Claim 2 (depends on 1)

The IC of claim 1 further comprising a second S/D region communicatively coupled to the channel stack.

### Claim 3 (depends on 2)

The IC of claim 2, wherein the tunnel further comprises a second set of end regions.

### Claim 4 (depends on 3)

The IC of claim 3, wherein the second set of end regions is closer to the second S/D region than the central region is to the second S/D region.

### Claim 5 (depends on 4)

The IC of claim 4, wherein the first type of WFM is formed in the second set of end regions.

### Claim 6 (depends on 1)

The IC of claim 1 further comprising inner spacers.

### Claim 7 (depends on 6)

The IC of claim 6, wherein a second portion of the boundary of the tunnel comprises a set of the inner spacers.

### Claim 8 (depends on 7)

The IC of claim 7, wherein:
the boundary of the tunnel further comprises a second one of the stacked, spaced-apart channel layers;
the second one of the stacked, spaced-apart channel layers comprises a second trimmed channel region and second non-trimmed channel regions; and
a third portion of the boundary of the tunnel is defined by the second trimmed channel region.

### Claim 9 (depends on 1)

The IC of claim 1 further comprising:
a gate dielectric within the tunnel;
wherein the first type of WFM comprises:
a first layer of metal having a first thickness;
a layer of an aluminum alloy; and
a second layer of metal;
wherein the second type of WFM comprises:
a third layer of metal having a second thickness;
a layer of an aluminum alloy; and
a fourth layer of metal; and
wherein the first thickness is less than the second thickness.

### Claim 10 (depends on 9)

The IC of claim 9, wherein the transistor devices comprise a second transistor type, the second transistor type comprising:
a second-transistor-type channel stack comprising second stacked, spaced-apart, channel layers;
wherein a first one of the second stacked, spaced-apart channel layers comprises a second trimmed channel region and second non-trimmed channel regions;
a second-transistor-type S/D region communicatively coupled to the second-transistor-type channel stack;
a second-transistor-type tunnel extending through the second-transistor-type channel stack;
wherein a first portion of a boundary of the second-transistor-type tunnel is defined by the second trimmed channel region;
a second-transistor-type gate dielectric within the second-transistor-type tunnel;
wherein the second-transistor-type tunnel comprises a second-transistor-type central region and a second-transistor-type set of end regions;
wherein the second-transistor-type set of end regions is closer to the second-transistor-type S/D region than the second-transistor-type central region is to the second-transistor-type S/D region;
a first type of second-transistor-type work-function metal (WFM) formed in the second-transistor-type set of end regions, the first WFM having a first work-function (WF); and
a second type of second-transistor-type WFM formed in the central region, the second type of WFM having a second WF;
wherein the first type of second-transistor-type WFM comprises a first layer of metal; and
wherein the second type of second-transistor-type WFM comprises:
a second layer of metal having a predetermined thickness;
a layer of an aluminum alloy; and
a third layer of metal;
wherein the predetermined thickness is greater than the second thickness.

### Claim 11

A method of forming an integrated circuit (IC) having transistor devices comprising a first transistor type, the method comprising forming the first transistor type by performing fabrication operations comprising:
forming a channel stack comprising first stacked, spaced-apart, channel layers;
wherein a first one of the first stacked, spaced-apart channel layers comprises a first trimmed channel region and first non-trimmed channel regions;
forming a first source or drain (S/D) region communicatively coupled to the channel stack;
forming a tunnel extending through the channel stack;
wherein a first portion of a boundary of the tunnel is defined by the first trimmed channel region;
wherein the tunnel comprises a central region and a first set of end regions;
wherein the first set of end regions is closer to the first S/D region than the central region is to the first S/D region;
forming a first type of work-function metal (WFM) in the first set of end regions, the first WFM having a first work-function (WF); and
forming a second type of WFM in the central region, the second type of WFM having a second WF;
wherein the first WF is different than the second WF.

### Claim 12 (depends on 11)

The method of claim 11 further comprising forming a second S/D region communicatively coupled to the channel stack.

### Claim 13 (depends on 12)

The method of claim 12, wherein the tunnel further comprises a second set of end regions.

### Claim 14 (depends on 13)

The method of claim 13, wherein the second set of end regions is closer to the second S/D region than the central region is to the second S/D region.

### Claim 15 (depends on 14)

The method of claim 14, wherein the first type of WFM is formed in the second set of end regions.

### Claim 16 (depends on 11)

The method of claim 11, wherein forming the tunnel comprises:
forming a set of inner spacers that extend under a gate structure of the transistor device; and
forming the first trimmed channel region.

### Claim 17 (depends on 16)

The method of claim 16, wherein the boundary of the tunnel comprises the set of the inner spacers.

### Claim 18 (depends on 17)

The method of claim 17, wherein:
the method further comprises forming a second one of the first stacked, spaced-apart channel layers;
wherein the second one of the first stacked, spaced-apart channel layers comprises a second trimmed channel region and second non-trimmed channel regions; and
the boundary of the tunnel further comprises the second trimmed channel region.

### Claim 19 (depends on 11)

The method of claim 11 further comprising:
forming a gate dielectric within the tunnel;
wherein the first type of WFM comprises:
a first layer of metal having a first thickness;
a layer of an aluminum alloy; and
a second layer of metal; and
wherein the second type of WFM comprises:
a third layer of metal having a second thickness;
a layer of an aluminum alloy; and
a fourth layer of metal;
wherein the first thickness is less than the second thickness.

### Claim 20 (depends on 19)

The method of claim 19, wherein the transistor devices comprise a second transistor type and the fabrication operations further comprise:
forming a second-transistor-type channel stack comprising stacked, spaced-apart, channel layers;
forming a second-transistor-type S/D region communicatively coupled to the second-transistor-type channel stack;
forming a second-transistor-type tunnel extending through the second-transistor-type channel stack;
forming a second-transistor-type gate dielectric within the second-transistor-type tunnel;
wherein the second-transistor-type tunnel comprises a second-transistor-type central region and a second-transistor-type set of end regions;
wherein the second-transistor-type set of end regions is closer to the second-transistor-type S/D region than the second-transistor-type central region is to the second-transistor-type S/D region;
forming a first type of second-transistor-type WFM formed in the second-transistor-type set of end regions, the first WFM having a first work-function (WF); and
forming a second type of second-transistor-type WFM formed in the central region, the second type of WFM having a second WF;
wherein the first type of second-transistor-type WFM comprises a first layer of metal; and
wherein the second type of second-transistor-type WFM comprises:
a second layer of metal having a predetermined thickness;
a layer of an aluminum alloy; and
a third layer of metal;
wherein the predetermined thickness is greater than the second thickness.