# US 12,191,350 B2 · Method of manufacturing semiconductor structure and semiconductor structure

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,191,350 B2
- Document ID: US12191350B2
- Status: Granted
- Kind: B2
- Application number: 17/805,510
- Filed: 2022-06-06
- Published: 2023-04-20
- Granted: 2025-01-07
- Earliest claimed: 2021-10-15
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Chih-Cheng Liu
- Web page: https://patentgrep.com/patent/US12191350B2

## CPC

- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10B 12/488: {Word lines}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/27: Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D 64/66: Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

The present disclosure provides a method of manufacturing a semiconductor structure, and a semiconductor structure. The method of manufacturing a semiconductor structure includes: providing a base, where a channel is formed in the base; forming a gate conductive layer, where the gate conductive layer covers a part of the channel; and forming a semiconductor doped layer, where the semiconductor doped layer fills the channel and covers the gate conductive layer, and a doping concentration of the semiconductor doped layer at a side close to a top surface of the gate conductive layer is different from a doping concentration of the semiconductor doped layer at a side away from the top surface of the gate conductive layer.

## Claims

### Claim 1

A method of manufacturing a semiconductor structure, comprising:
providing a base, wherein a channel is formed in the base;
forming a gate conductive layer, wherein the gate conductive layer covers a part of the channel; and
forming a semiconductor doped layer, wherein the semiconductor doped layer fills the channel and covers the gate conductive layer, and a doping concentration of the semiconductor doped layer at a side close to a top surface of the gate conductive layer is different from a doping concentration of the semiconductor doped layer at a side away from the top surface of the gate conductive layer.

### Claim 2 (depends on 1)

The method of manufacturing a semiconductor structure according to claim 1, wherein forming the semiconductor doped layer comprises:
forming a first semiconductor doped layer, wherein the first semiconductor doped layer covers the top surface of the gate conductive layer, and a top surface of the first semiconductor doped layer is lower than a top surface of the base; and
forming a second semiconductor doped layer, wherein the second semiconductor doped layer covers the top surface of the first semiconductor doped layer,
wherein a doping concentration of the second semiconductor doped layer is different from a doping concentration of the first semiconductor doped layer.

### Claim 3 (depends on 2)

The method of manufacturing a semiconductor structure according to claim 2, wherein the second semiconductor doped layer and the first semiconductor doped layer are of a same conductive type.

### Claim 4 (depends on 3)

The method of manufacturing a semiconductor structure according to claim 3, wherein the forming a first semiconductor doped layer comprises:
depositing a first semiconductor material, and performing first doping on the first semiconductor material to form a first doped region, wherein the first doped region covers the top surface of the gate conductive layer; and
performing second doping on the first semiconductor material to form a second doped region, wherein the second doped region covers a top surface of the first doped region,
wherein a doping concentration of the second doped region is different from a doping concentration of the first doped region.

### Claim 5 (depends on 2)

The method of manufacturing a semiconductor structure according to claim 2, wherein the forming a second semiconductor doped layer comprises:
depositing a second semiconductor material, and performing first doping on the second semiconductor material to form a third doped region, wherein the third doped region covers the top surface of the first semiconductor doped layer; and
performing second doping on the second semiconductor material to form a fourth doped region, wherein the fourth doped region covers a top surface of the third doped region,
wherein a doping concentration of the fourth doped region is different from a doping concentration of the third doped region.

### Claim 6 (depends on 2)

The method of manufacturing a semiconductor structure according to claim 2, wherein the doping concentration of the second semiconductor doped layer is greater than the doping concentration of the first semiconductor doped layer.

### Claim 7 (depends on 1)

The method of manufacturing a semiconductor structure according to claim 1, wherein the forming a gate conductive layer comprises:
filling the channel with an initial gate conductive layer; and
etching back the initial gate conductive layer, and retaining a part of the initial gate conductive layer having a height greater than or equal to ⅓ of a depth of the channel to form the gate conductive layer.

### Claim 8

A semiconductor structure, comprising:
a base, wherein the base comprises a channel;
a gate conductive layer, wherein the gate conductive layer covers a part of the channel; and
a semiconductor doped layer, wherein the semiconductor doped layer fills the channel and covers the gate conductive layer, and a doping concentration of the semiconductor doped layer at a side close to a top surface of the gate conductive layer is different from a doping concentration of the semiconductor doped layer at a side away from the top surface of the gate conductive layer.

### Claim 9 (depends on 8)

The semiconductor structure according to claim 8, wherein in a direction perpendicular to the base, a first height exists from a bottom of the gate conductive layer to a top of the semiconductor doped layer, the gate conductive layer has a second height, and the second height is greater than or equal to ⅓ of the first height.

### Claim 10 (depends on 9)

The semiconductor structure according to claim 9, wherein the semiconductor doped layer comprises:
a first semiconductor doped layer, wherein the first semiconductor doped layer covers a top surface of the gate conductive layer, and a top surface of the first semiconductor doped layer is lower than a top surface of the base; and
a second semiconductor doped layer, wherein the second semiconductor doped layer covers the top surface of the first semiconductor doped layer,
wherein a doping concentration of the second semiconductor doped layer is different from a doping concentration of the first semiconductor doped layer.

### Claim 11 (depends on 10)

The semiconductor structure according to claim 10, wherein the first semiconductor doped layer comprises a first dopant, the second semiconductor doped layer comprises a second dopant, and the first dopant and the second dopant are of a same conductive type.

### Claim 12 (depends on 11)

The semiconductor structure according to claim 11, wherein in the direction perpendicular to the base, a doping concentration of the first dopant in the first semiconductor doped layer changes gradually.

### Claim 13 (depends on 11)

The semiconductor structure according to claim 11, wherein in the direction perpendicular to the base, a doping concentration of the second dopant in the second semiconductor doped layer changes gradually.

### Claim 14 (depends on 11)

The semiconductor structure according to claim 11, wherein in the direction perpendicular to the base, the first semiconductor doped layer has a third height, the third height is less than or equal to ⅓ of the first height, the second semiconductor doped layer has a fourth height, and the fourth height is less than or equal to ⅓ of the first height.

### Claim 15 (depends on 10)

The semiconductor structure according to claim 10, wherein the doping concentration of the first semiconductor doped layer is less than the doping concentration of the second semiconductor doped layer.