# US 12,191,343 B2 · Semiconductor device and method of manufacturing semiconductor device

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- Number: US 12,191,343 B2
- Document ID: US12191343B2
- Status: Granted
- Kind: B2
- Application number: 18/107,085
- Filed: 2023-02-08
- Published: 2023-06-15
- Granted: 2025-01-07
- Earliest claimed: 2020-03-26
- Assignees: Lapis Semiconductor Co., Ltd.
- Applicants: Lapis Semiconductor Co., Ltd.
- Inventors: Takamitsu Furukawa
- Web page: https://patentgrep.com/patent/US12191343B2

## CPC

- H10D 1/20: Inductors
- H10W 20/497: {Inductive arrangements or effects of, or between, wiring layers}
- H10D 84/00: Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device including: a semiconductor substrate; a seed layer that is formed on the semiconductor substrate; and wiring that is formed on the seed layer and includes parallel row portions that are arranged at intervals from each other, and in which penetration passages that penetrate the parallel row portions in a direction in which the parallel rows lined up are formed in the parallel row portions.

## Claims

### Claim 1

A method of manufacturing a semiconductor device comprising:
forming a seed layer on a semiconductor substrate;
coating resist on the seed layer;
placing on the resist a mask component having a light shading portion that exposes the resist using a wiring pattern that represents a configuration of wiring while covering other portions of the resist, and linear portions that, when the configuration of the wiring is looked at in plan view, cover the resist over parallel row portions that are lined up at intervals from each other;
forming a resist pattern in which, while leaving the wiring pattern open by exposing the resist using the mask component, the resists that are lined up at intervals from each other so as to correspond to the parallel row portions are connected together linearly in a bottom portion of the openings by the linear portions;
forming wiring in the locations that have been opened by removing the resist from the seed layer in the resist pattern; and
removing the seed layer by etching.

### Claim 2 (depends on 1)

The method of manufacturing a semiconductor device according to claim 1, wherein the linear portions are formed as single linear bodies having a width that is less than a resolution limit of an exposure device.

### Claim 3 (depends on 1)

The method of manufacturing a semiconductor device according to claim 1, wherein the linear portions include a plurality of linear bodies that have a width that is less than the resolution limit of the exposure device, and are disposed at intervals from each other that are narrower than the resolution limit.