# US 12,191,322 B2 · Semiconductor device

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- Number: US 12,191,322 B2
- Document ID: US12191322B2
- Status: Granted
- Kind: B2
- Application number: 18/437,410
- Filed: 2024-02-09
- Published: 2024-08-08
- Granted: 2025-01-07
- Earliest claimed: 2011-09-30
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Atsushi Umezaki
- Web page: https://patentgrep.com/patent/US12191322B2

## CPC

- H10D 86/60: wherein the TFTs are in active matrices
- G09G 3/14: Semiconductor devices, e.g. diodes
- G09G 3/32: semiconductive, e.g. using light-emitting diodes [LED]
- G09G 3/36: using liquid crystals
- G11C 19/00: Digital stores in which the information is moved stepwise, e.g. shift registers
- H03B 1/00: Details
- H03K 3/00: Circuits for generating electric pulses; Monostable, bistable or multistable circuits (H03K4/00 takes precedence; for digital function generators in computers G06F1/02)
- H03K 17/6871: {the output circuit comprising more than one controlled field-effect transistor}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- G09G 2300/0426: Layout of electrodes and connections
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2330/021: Power management, e.g. power saving
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03B: GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS (generators adapted for electrophonic musical instruments G10H; masers or lasers H01S; generation of oscillations in plasma H05H)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.

## Claims

### Claim 1

A semiconductor device comprising:
a shift register circuit comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, one of a source and a drain of the sixth transistor, and a first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein a gate of the first transistor is electrically connected to one of a source and a drain of the third transistor, one of a source and a drain of the fourth transistor, and one of a source and a drain of the fifth transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the sixth transistor,
wherein a gate of the second transistor is electrically connected to a gate of the third transistor, one of a source and a drain of the seventh transistor, and one of a source and a drain of the eighth transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the fifth transistor,
wherein a gate of the fourth transistor is electrically connected to the other of the source and the drain of the fourth transistor and a third wiring,
wherein a gate of the fifth transistor is electrically connected to a fourth wiring,
wherein a gate of the sixth transistor is electrically connected to a fifth wiring,
wherein a gate of the seventh transistor is electrically connected to one of a source and a drain of the ninth transistor,
wherein the other of the source and the drain of the eighth transistor is electrically connected to the other of the source and the drain of the ninth transistor,
wherein a gate of the eighth transistor is electrically connected to a gate of the ninth transistor,
wherein a gate of the ninth transistor is electrically connected to one of a source and a drain of the tenth transistor and one of a source and a drain of the eleventh transistor,
wherein the first wiring is configured to transmit an output signal,
wherein the second wiring is configured to transmit a clock signal,
wherein the third wiring is configured to transmit a first signal,
wherein the fourth wiring is configured to transmit a second signal, and
wherein the fifth wiring is configured to transmit a third signal.

### Claim 2

A semiconductor device comprising:
a shift register circuit comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, one of a source and a drain of the sixth transistor, and a first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein a gate of the first transistor is electrically connected to one of a source and a drain of the third transistor, one of a source and a drain of the fourth transistor, and one of a source and a drain of the fifth transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the sixth transistor,
wherein a gate of the second transistor is electrically connected to a gate of the third transistor, one of a source and a drain of the seventh transistor, and one of a source and a drain of the eighth transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the fifth transistor,
wherein a gate of the fourth transistor is electrically connected to the other of the source and the drain of the fourth transistor and a third wiring,
wherein a gate of the fifth transistor is electrically connected to a fourth wiring,
wherein a gate of the sixth transistor is electrically connected to a fifth wiring,
wherein a gate of the seventh transistor is electrically connected to one of a source and a drain of the ninth transistor,
wherein the other of the source and the drain of the eighth transistor is electrically connected to the other of the source and the drain of the ninth transistor,
wherein a gate of the eighth transistor is electrically connected to a gate of the ninth transistor, and
wherein a gate of the ninth transistor is electrically connected to one of a source and a drain of the tenth transistor and one of a source and a drain of the eleventh transistor.

### Claim 3

A semiconductor device comprising:
a shift register circuit comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, one of a source and a drain of the sixth transistor, and a first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein a gate of the first transistor is electrically connected to one of a source and a drain of the third transistor, one of a source and a drain of the fourth transistor, and one of a source and a drain of the fifth transistor,
wherein a gate of the second transistor is electrically connected to a gate of the third transistor, one of a source and a drain of the seventh transistor, and one of a source and a drain of the eighth transistor,
wherein a gate of the fourth transistor is electrically connected to a third wiring,
wherein a gate of the fifth transistor is electrically connected to a fourth wiring,
wherein a gate of the seventh transistor is electrically connected to one of a source and a drain of the ninth transistor, and
wherein a gate of the eighth transistor is electrically connected to a gate of the ninth transistor.