# US 12,191,316 B2 · Semiconductor device

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- Number: US 12,191,316 B2
- Document ID: US12191316B2
- Status: Granted
- Kind: B2
- Application number: 18/439,855
- Filed: 2024-02-13
- Published: 2024-08-01
- Granted: 2025-01-07
- Earliest claimed: 2018-03-30
- Assignees: Japan Display Inc.
- Applicants: Japan Display Inc.
- Inventors: Tatsuya Toda; Toshinari Sasaki; Masayoshi Fuchi
- Web page: https://patentgrep.com/patent/US12191316B2

## CPC

- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- G02F 1/136227: {Through-hole connection of the pixel electrode to the active element through an insulation layer}
- G02F 1/136286: {Wiring, e.g. gate line, drain line}
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- G09F 9/30: in which the desired character or characters are formed by combining individual elements (panels comprising a number of electrodes in a single cell controlling light arriving from an independent light source, e.g. electro-optical or magneto-optical cell, G02F1/00)
- G09G 3/3225: using an active matrix
- G09G 3/3266: Details of drivers for scan electrodes
- H05B 33/02: Details
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 86/021: {of multiple TFTs}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- H10K 59/123: Connection of the pixel electrodes to the thin film transistors [TFT]
- H10K 59/124: Insulating layers formed between TFT elements and OLED elements
- H10K 59/131: Interconnections, e.g. wiring lines or terminals
- G02F 1/136295: {Materials; Compositions; Manufacture processes}
- G09G 2300/0426: Layout of electrodes and connections
- G09G 2300/0852: being a dynamic memory with more than one capacitor
- G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10K 59/1201: {Manufacture or treatment}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G09F: DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- H05B: ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

A semiconductor device including: a first gate electrode; a first gate insulating layer on the first gate electrode; a first oxide semiconductor layer on the first insulating layer; source and drain electrodes connected to the first oxide semiconductor layer; a second gate insulating layer on the first oxide semiconductor layer; a second oxide semiconductor layer on the second gate insulating layer; a second gate electrode on the second oxide semiconductor layer, the second gate electrode being in contact with the second oxide semiconductor layer; a first insulating layer on the second gate electrode, the first insulating layer having a part of a first aperture overlapping with the second oxide semiconductor layer in a planar view; and a first connecting electrode electrically connecting the first gate electrode and the second gate electrode via the first aperture.

## Claims

### Claim 1

A semiconductor device comprising:
a first gate electrode;
a first gate insulating layer above the first gate electrode;
a first oxide semiconductor layer above the first gate insulating layer;
a source electrode and a drain electrode connected to the first oxide semiconductor layer;
a second gate insulating layer above the first oxide semiconductor layer;
a second gate electrode above the second gate insulating layer;
a first insulating layer above the second gate electrode;
a second oxide semiconductor layer between the second gate insulating layer and the second gate electrode;
a first aperture penetrating the first insulating layer and the second gate insulating layer, a part of the first aperture overlapping the second oxide semiconductor layer in a planar view;
a first connecting electrode in the first aperture;
a second aperture penetrating the first gate insulating layer; and
a second connecting electrode in the second aperture,
wherein
the first connecting electrode is connected to the second gate electrode and the second connecting electrode, and
the second connecting electrode is connected to the first gate electrode.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the first connecting electrode covers a side surface of the second oxide semiconductor layer in the first aperture.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the second connecting electrode is in a same layer with the source electrode or the drain electrode.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein
the second connecting electrode is in contact with a top surface of the first gate insulating layer, and
the source electrode or the drain electrode is in contact with a top surface of the first gate insulating layer.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the first connecting electrode is in contact with the second oxide semiconductor layer.