# US 12,191,313 B2 · Semiconductor device and method for manufacturing the same

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- Number: US 12,191,313 B2
- Document ID: US12191313B2
- Status: Granted
- Kind: B2
- Application number: 18/142,206
- Filed: 2023-05-02
- Published: 2023-08-24
- Granted: 2025-01-07
- Earliest claimed: 2012-01-26
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Shunpei Yamazaki
- Web page: https://patentgrep.com/patent/US12191313B2

## CPC

- H10D 86/60: wherein the TFTs are in active matrices
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6756: {Amorphous oxide semiconductors}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/40: Crystalline structures
- H10D 62/80: characterised by the materials
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/425: {having different crystal properties in different TFTs or within an individual TFT}
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10F 39/026: {Wafer-level processing}
- H10P 14/3434: {being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424)}
- H10P 14/3806: {using crystallisation-enhancing elements}
- H10B 41/70: the floating gate being an electrode shared by two or more components
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A region containing a high proportion of crystal components and a region containing a high proportion of amorphous components are formed separately in one oxide semiconductor film. The region containing a high proportion of crystal components is formed so as to serve as a channel formation region and the other region is formed so as to contain a high proportion of amorphous components. It is preferable that an oxide semiconductor film in which a region containing a high proportion of crystal components and a region containing a high proportion of amorphous components are mixed in a self-aligned manner be formed. To separately form the regions which differ in crystallinity in the oxide semiconductor film, first, an oxide semiconductor film containing a high proportion of crystal components is formed and then process for performing amorphization on part of the oxide semiconductor film is conducted.

## Claims

### Claim 1

A semiconductor device comprising:
a silicon layer comprising a first channel formation region of a first transistor;
a first insulating film over the silicon layer;
a first conductive layer over the first insulating film;
a second insulating film in contact with a side surface of the first conductive layer;
a third insulating film in contact with an upper surface of the second insulating film;
a second conductive layer in contact with an upper surface of the third insulating film;
a third conductive layer in contact with the upper surface of the third insulating film;
an oxide semiconductor layer in contact with the second conductive layer and the third conductive layer, the oxide semiconductor layer comprising a second channel formation region of a second transistor;
a fourth insulating film over the second channel formation region;
a fourth conductive layer over the fourth insulating film;
a fifth insulating film in contact with an upper surface of the fourth conductive layer; and
a fifth conductive layer in contact with an upper surface of the fifth insulating film, the fifth conductive layer overlapping with the third conductive layer,
wherein the second conductive layer is configured to serve as one of a source electrode and a drain electrode of the second transistor,
wherein the third conductive layer is configured to serve as the other of the source electrode and the drain electrode of the second transistor,
wherein an upper surface of the first conductive layer is in contact with the third conductive layer,
wherein the fifth conductive layer overlaps with the first channel formation region, and
wherein the fifth conductive layer comprises a region extending in a direction intersecting with a channel length direction of the second transistor.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises indium and zinc.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the fifth conductive layer comprises a region extending in a direction intersecting with a channel length direction of the first transistor.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the fifth conductive layer does not overlap with the second channel formation region.

### Claim 6

A semiconductor device comprising:
a silicon layer comprising a first channel formation region of a first transistor;
a first insulating film over the silicon layer;
a first conductive layer over the first insulating film;
a second insulating film in direct contact with a side surface of the first conductive layer;
a third insulating film in direct contact with an upper surface of the second insulating film;
a second conductive layer in direct contact with an upper surface of the third insulating film;
a third conductive layer in direct contact with the upper surface of the third insulating film;
an oxide semiconductor layer in direct contact with the second conductive layer and the third conductive layer, the oxide semiconductor layer comprising a second channel formation region of a second transistor;
a fourth insulating film over the second channel formation region;
a fourth conductive layer over the fourth insulating film;
a fifth insulating film in direct contact with an upper surface of the fourth conductive layer; and
a fifth conductive layer in direct contact with an upper surface of the fifth insulating film, the fifth conductive layer overlapping with the third conductive layer,
wherein the second conductive layer is configured to serve as one of a source electrode and a drain electrode of the second transistor,
wherein the third conductive layer is configured to serve as the other of the source electrode and the drain electrode of the second transistor,
wherein an upper surface of the first conductive layer is in direct contact with the third conductive layer,
wherein the fifth conductive layer overlaps with the first channel formation region, and
wherein the fifth conductive layer comprises a region extending in a direction intersecting with a channel length direction of the second transistor.

### Claim 7 (depends on 6)

The semiconductor device according to claim 6, wherein the oxide semiconductor layer comprises indium and zinc.

### Claim 8 (depends on 6)

The semiconductor device according to claim 6, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

### Claim 9 (depends on 6)

The semiconductor device according to claim 6, wherein the fifth conductive layer comprises a region extending in a direction intersecting with a channel length direction of the first transistor.

### Claim 10 (depends on 6)

The semiconductor device according to claim 6, wherein the fifth conductive layer does not overlap with the second channel formation region.

### Claim 11

A semiconductor device comprising:
a silicon layer comprising a first channel formation region of a first transistor;
a first insulating film over the silicon layer;
a first conductive layer over the first insulating film;
a second insulating film in direct contact with a side surface of the first conductive layer;
a third insulating film in direct contact with an upper surface of the second insulating film;
a second conductive layer in direct contact with an upper surface of the third insulating film;
a third conductive layer in direct contact with the upper surface of the third insulating film;
an oxide semiconductor layer in direct contact with the second conductive layer and the third conductive layer, the oxide semiconductor layer comprising a second channel formation region of a second transistor;
a fourth insulating film over the second channel formation region;
a fourth conductive layer over the fourth insulating film;
a fifth insulating film in direct contact with an upper surface of the fourth conductive layer; and
a fifth conductive layer in direct contact with an upper surface of the fifth insulating film, the fifth conductive layer overlapping with the third conductive layer,
wherein the second conductive layer is configured to serve as one of a source electrode and a drain electrode of the second transistor,
wherein the third conductive layer is configured to serve as the other of the source electrode and the drain electrode of the second transistor,
wherein an upper surface of the first conductive layer is in direct contact with the third conductive layer,
wherein the fifth conductive layer overlaps with the first channel formation region and the first conductive layer, and
wherein the fifth conductive layer comprises a region extending in a direction intersecting with a channel length direction of the second transistor.

### Claim 12 (depends on 11)

The semiconductor device according to claim 11, wherein the oxide semiconductor layer comprises indium and zinc.

### Claim 13 (depends on 11)

The semiconductor device according to claim 11, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

### Claim 14 (depends on 11)

The semiconductor device according to claim 11, wherein the fifth conductive layer comprises a region extending in a direction intersecting with a channel length direction of the first transistor.

### Claim 15 (depends on 11)

The semiconductor device according to claim 11, wherein the fifth conductive layer does not overlap with the second channel formation region.