Logic cell with small cell delay

A semiconductor structure, comprising:

• a semiconductor substrate;
• and
• a logic cell with a logic function, and comprising:
• a plurality of first transistors in an active region over the semiconductor substrate, comprising first gate electrodes extending along a first direction;
• a second transistor in the active region, comprising a second gate electrode extending along the first direction;
• a third transistor in the active region, comprising a third gate electrode extending along the first direction;
• and
• a first isolation structure and a second isolation structure on opposite edges of the active region and extending along the first direction,
• wherein the first gate electrodes are disposed between the first and second isolation structures, the second gate electrode is disposed between the first gate electrodes and the first isolation structure, and the third gate electrode is disposed between the first gate electrodes and the second isolation structure,
• wherein the first and second isolation structures and the first gate electrode have a first length in the first direction, and the second and third gate electrodes have a second length in the first direction, and the second length is shorter than the first length, wherein the first transistors are configured to perform the logic function, and the second and third transistors are dummy transistors.