# US 12,191,308 B2 · Non-planar semiconductor device having doped sub-fin region and method to fabricate same

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- Number: US 12,191,308 B2
- Document ID: US12191308B2
- Status: Granted
- Kind: B2
- Application number: 18/185,728
- Filed: 2023-03-17
- Published: 2023-07-13
- Granted: 2025-01-07
- Earliest claimed: 2018-08-14
- Assignees: Tahoe Research, Ltd.
- Applicants: Tahoe Research, Ltd.
- Inventors: Tahir Ghani; Salman Latif; Chanaka D. Munasinghe
- Web page: https://patentgrep.com/patent/US12191308B2

## CPC

- H10D 84/853: {comprising FinFETs}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0241: {doping of vertical sidewalls, e.g. using tilted or multi-angled implants}
- H10D 30/6215: {having multiple independently-addressable gate electrodes}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 30/28: characterised by an annealing step, e.g. for activation of dopants
- H10P 32/141: {the applied layer comprising oxides only}
- H10P 32/171: {being group IV material}
- H10P 95/06: {Planarisation of inorganic insulating materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.

## Claims

### Claim 1

An integrated circuit structure, comprising:
a first fin of a first semiconductor material, the first fin having a lower fin portion and an upper fin portion;
a first dielectric layer comprising a first dielectric material, the first dielectric layer along sidewalls of the lower fin portion of the first fin but not along sidewalls of the upper fin portion of the first fin;
a first insulating layer comprising a second dielectric material different from the first dielectric material, the first insulating layer over the first dielectric layer;
a dielectric fill material over the first insulating layer, wherein a portion of the upper fin portion of the first fin extends above a top surface of the dielectric fill material; and
a gate electrode, wherein the gate electrode is over a top of the first fin and the dielectric fill material and laterally adjacent to sidewalls of the upper fin portion of the first fin.

### Claim 2 (depends on 1)

The integrated circuit structure of claim 1, wherein the first dielectric layer is conformal to the sidewalls of the lower fin portion of the first fin.

### Claim 3 (depends on 2)

The integrated circuit structure of claim 2, wherein the first dielectric layer comprises a first dopant of a first conductivity.

### Claim 4 (depends on 2)

The integrated circuit structure of claim 2, wherein the first insulating layer is spaced apart from the sidewalls of the lower fin portion of the first fin by the first dielectric layer.

### Claim 5 (depends on 4)

The integrated circuit structure of claim 4, wherein the first insulating layer is in direct contact with and conformal to the first dielectric layer.

### Claim 6 (depends on 3)

The integrated circuit structure of claim 3, wherein the first dielectric layer comprises silicon and oxygen and the first insulating blocking layer comprises nitrogen.

### Claim 7 (depends on 1)

The integrated circuit structure of claim 1, further comprising a second fin of a second semiconductor material, the second fin having a lower fin portion and an upper fin portion, wherein the upper fin portion of the second fin is above the top surface of the dielectric fill material and the gate electrode over a top of second fin and laterally adjacent to sidewalls of the upper fin portion of the second fin.

### Claim 8 (depends on 7)

The integrated circuit structure of claim 7, wherein the first insulating layer is over sidewalls of the lower fin portion of the second fin.

### Claim 9 (depends on 8)

The integrated circuit structure of claim 8, wherein the first insulating layer is conformal to the sidewall of the lower fin portion of the second fin.

### Claim 10 (depends on 9)

The integrated circuit structure of claim 9, wherein the first insulating layer is in direct contact with the sidewalls of the lower fin portion of the second fin.

### Claim 11 (depends on 8)

The integrated circuit structure of claim 8, wherein the first insulating layer is in direct contact with and conformal to the first dielectric layer along the sidewalls of the lower fin portion of the first fin and wherein the first insulating layer is in direct contact with and conformal to the sidewalls of the lower fin portion of the second fin.

### Claim 12 (depends on 11)

The integrated circuit structure of claim 11, wherein the first insulating layer extends continuously from a sidewall of the lower fin portion of the first fin to a sidewall of the lower fin portion of the second fin.

### Claim 13 (depends on 7)

The integrated circuit structure of claim 7, further comprising:
a second dielectric layer comprising a third dielectric material, the second dielectric layer along the sidewalls of the lower fin portion of the second fin; and
a second insulating layer comprising a fourth dielectric material different from the third dielectric material, the second insulating layer over the second dielectric layer.

### Claim 14 (depends on 13)

The integrated circuit structure of claim 13, wherein the first dielectric layer comprises a first dopant of a first conductivity and the second dielectric layer comprises a second dopant of a second conductivity different from the first conductivity.

### Claim 15 (depends on 13)

The integrated circuit structure of claim 13, wherein the second dielectric layer is in direct contact with and conformal to the sidewalls of the lower fin portion of the second fin and the second insulating layer is spaced apart from the lower fin portion of the second fin by the second dielectric layer.

### Claim 16 (depends on 15)

The integrated circuit structure of claim 15, wherein the first insulating layer is in direct contact with and conformal to the second insulating layer along the sidewalls of the lower fin portion of the second fin.

### Claim 17 (depends on 15)

The integrated circuit structure of claim 15, wherein the second insulating layer is in direct contact with and conformal to the second dielectric layer along the sidewalls of the lower fin portion of the second fin.

### Claim 18 (depends on 17)

The integrated circuit structure of claim 17, wherein the first insulating layer is in direct contact with and conformal to the second insulating layer along the sidewalls of the lower fin portion of the second fin.

### Claim 19 (depends on 18)

The integrated circuit structure of claim 18, wherein the first insulating layer extends continuously from a sidewall of the lower fin portion of the first fin to a sidewall of the lower fin portion of the second fin.

### Claim 20 (depends on 14)

The integrated circuit structure of claim 14, wherein the first and second dielectric layers comprise silicon and oxygen and the first and second insulating layers comprise nitrogen.