# US 12,191,304 B2 · Method of manufacturing a semiconductor device and a semiconductor device

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- Number: US 12,191,304 B2
- Document ID: US12191304B2
- Status: Granted
- Kind: B2
- Application number: 18/200,331
- Filed: 2023-05-22
- Published: 2023-09-21
- Granted: 2025-01-07
- Earliest claimed: 2016-11-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Tung Ying Lee; Ziwei Fang; Yee-Chia Yeo; Meng-Hsuan Hsiao
- Web page: https://patentgrep.com/patent/US12191304B2

## CPC

- H10D 84/834: {comprising FinFETs}
- A61B 17/285: combined with cutting implements
- A61B 17/29: Forceps for use in minimally invasive surgery
- A61B 17/295: combined with cutting implements
- A61B 18/1445: {at the distal end of a shaft, e.g. forceps or scissors at the end of a rigid rod}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/666: {the conductor further comprising additional layers}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0696: {by using sacrificial placeholders, e.g. using sacrificial plugs}
- H10W 20/076: {in via holes or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- A61B 2017/2825: {Inserts of different material in jaws}
- A61B 2017/2926: {Details of heads or jaws}
- A61B 2018/00589: {Coagulation}
- A61B 2018/0063: {Sealing}
- A61B 2018/1455: {having a moving blade for cutting tissue grasped by the jaws}
- A61B 2018/1465: {Deformable electrodes}
- A61B 2090/034: {abutting on parts of the device itself}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/834: further characterised by the dopants
- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- A61B: DIAGNOSIS; SURGERY; IDENTIFICATION (usefulness limited to only animals A61D)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In a method of forming a FinFET, a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is recessed so that a remaining layer of the first sacrificial layer is formed on the isolation insulating layer and an upper portion of the source/drain structure is exposed. A second sacrificial layer is formed on the remaining layer and the exposed source/drain structure. The second sacrificial layer and the remaining layer are patterned, thereby forming an opening. A dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first and second sacrificial layers are removed to form a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.

## Claims

### Claim 1

A semiconductor device, comprising:
a fin structure extending in a first direction;
an isolation insulating layer from which the fin structure protrudes;
a source/drain epitaxial layer disposed over the fin structure;
a source/drain contact in contact with the source/drain epitaxial layer; and
a gate structure extending in a second direction crossing the first direction and including a gate electrode and a gate cap insulating layer,
wherein in a cross section cutting the fin structure along the first direction, the source/drain contact has a top width greater than a bottom width, and
in a cross section along the first direction, opposite sides of a top of the gate cap insulating layer are recessed such that a top width of the gate cap insulating layer is smaller than a bottom width of the gate cap insulating layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the source/drain contact is in contact with the gate cap insulating layer.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, further comprising a gate sidewall spacer disposed on a sidewall of the gate structure.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the gate sidewall spacer only partially covers a sidewall of the gate cap insulating layer.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising a dielectric layer disposed at a side of the gate structure in the first direction and at a side of the source/drain contact in the second direction.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein in a cross section along the first direction, the dielectric layer has a top width greater than a bottom width.

### Claim 7 (depends on 5)

The semiconductor device of claim 5, wherein the dielectric layer includes a first dielectric layer in contact with the source/drain contact and a second dielectric layer disposed on the first dielectric layer and separated from the source/drain contact by the first dielectric layer.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the second dielectric layer is in contact with the gate cap insulating layer.

### Claim 9 (depends on 7)

The semiconductor device of claim 7, wherein the second dielectric layer comprises a silicon nitride based material.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the second dielectric layer further comprises GeO.

### Claim 11 (depends on 7)

The semiconductor device of claim 7, wherein the first dielectric layer comprises GeO.

### Claim 12

A semiconductor device, comprising:
a first FinFET including a first fin structure, a first source/drain epitaxial layer, a first source/drain contact disposed over the first source/drain epitaxial layer;
a second FinFET disposed adjacent to the first FinFET and including a second fin structure, a second source/drain epitaxial layer and a second source/drain contact disposed over the second source/drain epitaxial layer; and
a dielectric layer separating the first source/drain contact and the second source/drain contact, wherein:
the first and second fin structures extend in a first direction,
the first FinFET and the second FinFET share a gate structure extending in a second direction crossing the first direction and including a gate electrode layer and a gate cap insulating layer,
in a cross section cutting the first fin structure along the first direction, the first source/drain contact has a funnel shape having a wider top than a body region, and
in a cross section of the first FinFET along the first direction, opposite sides of a top of the gate cap insulating layer are recessed such that a top width of the gate cap insulating layer is smaller than a bottom width of the gate cap insulating layer.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein in a cross section cutting the dielectric layer along the first direction, the dielectric layer has a funnel shape having a wider top than a body region.

### Claim 14 (depends on 12)

The semiconductor device of claim 12, wherein the dielectric layer includes a first dielectric layer in contact with the first and second source/drain contacts and a second dielectric layer disposed on the first dielectric layer.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the second dielectric layer is in contact with the gate cap insulating layer.

### Claim 16 (depends on 14)

The semiconductor device of claim 14, wherein the second dielectric layer comprises a silicon nitride based material.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein the second dielectric layer further comprises GeO.

### Claim 18 (depends on 14)

The semiconductor device of claim 14, wherein the first dielectric layer comprises GeO.

### Claim 19

A semiconductor device, comprising:
a first FinFET including a first fin structure, a first gate structure, a first source/drain epitaxial layer, a first source/drain contact disposed over the first source/drain epitaxial layer;
a second FinFET disposed adjacent to the first FinFET and including a second fin structure, a second gate structure, a second source/drain epitaxial layer and a second source/drain contact disposed over the second source/drain epitaxial layer; and
a dielectric layer separating the first source/drain contact and the second source/drain contact, wherein:
the first and second fin structures extend in a first direction,
the first and second gate structures extend in a second direction crossing the first direction,
in a cross section cutting the first fin structure along the first direction, the first source/drain contact has a funnel shape having a wider top than a body region, and
in a cross section of the first FinFET along the first direction, opposite sides of a top of a gate cap insulating layer are recessed such that a top width of the gate cap insulating layer is smaller than a bottom width of the gate cap insulating layer.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein the dielectric layer comprises germanium.