# US 12,191,303 B2 · Semiconductor device structure

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- Number: US 12,191,303 B2
- Document ID: US12191303B2
- Status: Granted
- Kind: B2
- Application number: 18/635,399
- Filed: 2024-04-15
- Published: 2024-08-01
- Granted: 2025-01-07
- Earliest claimed: 2021-10-29
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Hsih-Yang Chiu
- Web page: https://patentgrep.com/patent/US12191303B2

## CPC

- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 10/031: {of isolation regions comprising PN junctions}
- H10W 10/30: Isolation regions comprising PN junctions
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/43: Layouts of interconnections
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/90: Bond pads, in general
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device structure including a doped region under an isolation feature is provided. The semiconductor device structure includes a first substrate, a first well region, a first gate structure, a second gate structure, a first doped region, and a first conductive feature. The substrate has a first surface and a second surface opposite to the first surface. The first well region is in the first substrate. The first well region has a first conductive type. The first gate structure is disposed on the second surface. The second gate structure is disposed on the second surface. The first doped region includes a second conductive type different from the first conductive type. The first doped region is disposed between the first gate structure and the second gate structure. The first conductive feature extends between the first surface of the first substrate and the first doped region.

## Claims

### Claim 1

A semiconductor device structure, comprising:
a substrate having an active surface and a backside surface;
a first well region in the substrate, wherein the first well region has a first conductive type;
a first transistor adjacent to the active surface of the substrate;
a second transistor adjacent to the active surface of the substrate;
a first doped region with a second conductive type different from the first conductive type, wherein the first doped region is disposed in the first well region and between the first transistor and the second transistor; and
a circuit structure on the backside surface of the substrate, wherein the circuit structure is configured to transmit or provide a voltage electrically coupled with the first doped region.

### Claim 2 (depends on 1)

The semiconductor device structure of claim 1, further comprising:
a first conductive feature exposed from the backside surface of the substrate, wherein the first conductive feature electrically connects the circuit structure and the first doped region.

### Claim 3 (depends on 2)

The semiconductor device structure of claim 2, further comprising:
a conductive structure extending from the active surface of the substrate, wherein the conductive structure is electrically coupled with the first doped region.

### Claim 4 (depends on 3)

The semiconductor device structure of claim 3, further comprising:
a first isolation feature disposed in the substrate and between the first transistor and the second transistor, wherein the conductive structure penetrates the isolation feature.

### Claim 5 (depends on 3)

The semiconductor device structure of claim 3, wherein the conductive structure is vertically aligned to the first conductive feature.

### Claim 6 (depends on 2)

The semiconductor device structure of claim 2, further comprising:
a second well region in the substrate and surrounding the first doped region; and
a third well region spaced apart from the active surface of the substrate and in contact with the second well region.

### Claim 7 (depends on 6)

The semiconductor device structure of claim 6, wherein first conductive feature penetrates the third well region.

### Claim 8 (depends on 7)

The semiconductor device structure of claim 7, wherein each of the second well region and the third well region has the second conductive type.

### Claim 9 (depends on 4)

The semiconductor device structure of claim 4, wherein a lateral surface of the circuit structure and a lateral surface of the substrate are discontinuous.