# US 12,191,301 B2 · Integrated circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,191,301 B2 - Document ID: US12191301B2 - Status: Granted - Kind: B2 - Application number: 17/853,698 - Filed: 2022-06-29 - Published: 2022-10-20 - Granted: 2025-01-07 - Earliest claimed: 2020-02-02 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.; Tsmc China Company Limited - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.; Tsmc China Company Limited - Inventors: Ya-Qi Ma; Lei Pan; Zhen Tang - Web page: https://patentgrep.com/patent/US12191301B2 ## CPC - H10D 89/811: {using FETs as protective elements} - H10D 84/40: characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs - H10D 89/921: {characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses} - H10D 84/80: characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs (H10D84/40 takes precedence) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract An integrated circuit includes first to second transistors and a resistive device. The first transistor is coupled between a pad and a first voltage terminal that provides a first supply voltage. The second transistor is coupled in parallel with the first transistor. A breakdown voltage of the first transistor is different from a trigger voltage of the second transistor. The resistive device is coupled between the pad and a second voltage terminal that provides a second supply voltage higher than the first supply voltage, and operates with the second supply voltage in an electrostatic discharge (ESD) event when the first and second transistors discharge a ESD current between the pad and the first voltage terminal. ## Claims ### Claim 1 An integrated circuit, comprising: a first transistor coupled between a pad and a first voltage terminal that provides a first supply voltage; a second transistor coupled in parallel with the first transistor, wherein a breakdown voltage of the first transistor is different from a trigger voltage of the second transistor; and a resistive device coupled between the pad and a second voltage terminal that provides a second supply voltage higher than the first supply voltage, wherein the resistive device is configured to operate with the second supply voltage in an electrostatic discharge (ESD) event when the first and second transistors are configured to discharge a ESD current between the pad and the first voltage terminal. ### Claim 2 (depends on 1) The integrated circuit of claim 1, wherein the breakdown voltage of the first transistor is greater than the trigger voltage of the second transistor. ### Claim 3 (depends on 2) The integrated circuit of claim 2, wherein each of the first and second transistors has a first active region that is coupled to the pad and has a first width, and the resistive device has a second active region that is coupled to the first active regions of the first and second transistors and has a second width smaller than the first width. ### Claim 4 (depends on 1) The integrated circuit of claim 1, further comprising: a plurality of third transistors coupled between the first transistor and the first voltage terminal, wherein a breakdown voltage of each of the plurality of third transistors is smaller than the breakdown voltage of the first transistor. ### Claim 5 (depends on 4) The integrated circuit of claim 4, further comprising: a fourth transistor coupled between the second transistor and the first voltage terminal, wherein the fourth transistor is diode-connected. ### Claim 6 (depends on 1) The integrated circuit of claim 1, wherein the first and second transistors are of a first conductivity type, and the first transistor is disposed in a well region of the first conductivity type and separated from the second transistor by a substrate. ### Claim 7 (depends on 6) The integrated circuit of claim 6, wherein the resistive device comprises: a plurality of active regions of a second conductivity type different from the first conductivity type. ### Claim 8 (depends on 1) The integrated circuit of claim 1, wherein the second transistor is configured to be triggered to discharge the ESD current after the first transistor is turned on. ### Claim 9 A method, comprising: forming first to second active regions, that are of a first conductivity type, coupled between a pad and a first voltage terminal, wherein the first to second active regions have different widths; forming a first gate interposed between the first to second active regions to form a first transistor; forming third to fourth active regions, that are of the first conductivity type, coupled between the pad and the first voltage terminal; forming a second gate interposed between the third to fourth active regions to form a second transistor; and forming a first conductive segment that is coupled to the first and third active regions and configured to transmit an electrostatic discharge (ESD) current from the pad to the first active region and to the third active region. ### Claim 10 (depends on 9) The method of claim 9, wherein a width of the first active region, coupled to the pad, is greater than a width of the second active region, and a width of the third active region, coupled to the pad, is greater than a width of the fourth active region. ### Claim 11 (depends on 9) The method of claim 9, further comprising: forming a plurality of fifth active regions coupled between the second active region and the first voltage terminal, wherein a width of the plurality of fifth active regions is smaller than a width of the first active region coupled to the pad. ### Claim 12 (depends on 9) The method of claim 9, further comprising: forming a plurality of fifth active regions of the first conductivity type that are in a well of a second conductivity type different from the first conductivity type and coupled between the first active region and a second voltage terminal, wherein widths of the plurality of fifth active regions are smaller than a width of the first active region. ### Claim 13 (depends on 12) The method of claim 12, wherein the plurality of fifth active regions are separated from each other. ### Claim 14 (depends on 9) The method of claim 9, further comprising: forming a fifth active region coupled between the fourth active region and the first voltage terminal; forming a third gate interposed between the fourth to fifth active regions to form a third transistor; and forming a second conductive segment to couple the third gate to the fifth active region. ### Claim 15 (depends on 9) The method of claim 9, further comprising: forming a resistive structure coupled between the first active region and a second voltage terminal different from the first voltage terminal, wherein the first to second active regions are disposed in a well that is of a same conductivity type of the first to second active regions. ### Claim 16 An integrated circuit, comprising: a first transistor comprises a first active region coupled between a first voltage terminal and a pad; a second transistor comprising a second active region coupled between the pad and the first voltage terminal, wherein the first and second transistors are configured to discharge a first electrostatic discharge (ESD) current; and a third transistor comprising a third active region coupled between the pad and a second voltage terminal different from the first voltage terminal, and configured to discharge a second electrostatic discharge current, wherein a width of the third active region is smaller than that of the first and second active region. ### Claim 17 (depends on 16) The integrated circuit of claim 16, wherein the first to second transistors are of a first conductivity type, and the third transistor is of a second conductivity type different from the first conductivity type. ### Claim 18 (depends on 16) The integrated circuit of claim 16, further comprising: a fourth transistor coupled between the second transistor and the first voltage terminal, wherein gate and source terminals of the fourth transistor are coupled to the first voltage terminal. ### Claim 19 (depends on 18) The integrated circuit of claim 18, wherein the fourth transistor comprises a plurality of fourth active regions, wherein widths of the plurality of fourth active regions are smaller than a width of the second active region. ### Claim 20 (depends on 16) The integrated circuit of claim 16, further comprising: a plurality of fourth transistors coupled between the first transistor and the first voltage terminal, wherein a breakdown voltage of each of the plurality of fourth transistors is smaller than a breakdown voltage of the first transistor, and a width of each in a plurality of fourth active regions included in the plurality of fourth transistors is smaller than the first active region.