# US 12,191,300 B2 · Integrated circuit structure with resistive semiconductor material for back well > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,191,300 B2 - Document ID: US12191300B2 - Status: Granted - Kind: B2 - Application number: 17/662,921 - Filed: 2022-05-11 - Published: 2023-11-16 - Granted: 2025-01-07 - Earliest claimed: 2022-05-11 - Assignees: GlobalFoundries U.S. Inc. - Applicants: GlobalFoundries U.S. Inc. - Inventors: Robert J. Gauthier, Jr.; Rajendran Krishnasamy; Anupam Dutta; Anindya Nath; Xiangxiang Lu; Satyasuresh Vvss Choppalli; Lin Lin - Web page: https://patentgrep.com/patent/US12191300B2 ## CPC - H10D 89/713: {including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices} - H10D 89/811: {using FETs as protective elements} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Embodiments of the disclosure provide an integrated circuit (IC) structure with resistive semiconductor material for a back well. The IC structure may include a semiconductor substrate having a deep well, and a device within a first portion of the deep well. The device includes a first doped semiconductor material coupled to a first contact, and a second doped semiconductor material coupled to a second contact. The deep well couples the first doped semiconductor material to the second doped semiconductor material. A first back well is within a second portion of the deep well. A first resistive semiconductor material is within the deep well and defines a boundary between the first portion of the deep well and the second portion of the deep well. ## Claims ### Claim 1 An integrated circuit (IC) structure comprising: a semiconductor substrate having a deep well; a device within a first portion of the deep well, the device including: a first doped semiconductor material coupled to a first contact; a second doped semiconductor material coupled to a second contact, wherein the deep well couples the first doped semiconductor material to the second doped semiconductor material; a first back well within a second portion of the deep well; and a first resistive semiconductor material within the deep well and interposed between the first portion of the deep well and the second portion of the deep well. ### Claim 2 (depends on 1) The IC structure of claim 1, further comprising a trench isolation (TI) within the deep well and horizontally between the first back well and the device, wherein the first resistive semiconductor material is below a lower surface of the first back well and horizontally adjacent the TI. ### Claim 3 (depends on 1) The IC structure of claim 1, wherein the first resistive semiconductor material includes amorphous silicon (a-Si). ### Claim 4 (depends on 1) The IC structure of claim 1, further comprising: a second back well within a third portion of the deep well, wherein the first portion of the deep well is horizontally between the second portion and the third portion of the deep well; and a second resistive semiconductor material within the deep well and interposed between the first portion of the deep well and the third portion of the deep well. ### Claim 5 (depends on 1) The IC structure of claim 1, wherein the device includes a transistor including: a source within the first doped semiconductor material, a drain within the second doped semiconductor material, and a gate over the first portion of the deep well, wherein the gate is horizontally between the first doped semiconductor material and the second doped semiconductor material. ### Claim 6 (depends on 1) The IC structure of claim 1, wherein the device includes an electrostatic discharge device (ESD) including: a first n-type semiconductor within the first doped semiconductor material, a second n-type semiconductor within the second doped semiconductor material, and a p-type semiconductor within the first portion of the deep well, wherein the p-type semiconductor is horizontally between the first n-type semiconductor and the second n-type semiconductor. ### Claim 7 (depends on 1) The IC structure of claim 1, wherein the device includes a silicon controlled rectifier (SCR) including: An n-type semiconductor within the first doped semiconductor material, a shallow well within the deep well, and a p-type semiconductor within the shallow well, wherein the second doped semiconductor material includes a gate semiconductor within the shallow well, a trench isolation (TI) horizontally separates the gate semiconductor from the p-type semiconductor, and the first portion of the deep well is horizontally between the n-type semiconductor and the shallow well. ### Claim 8 An integrated circuit (IC) structure comprising: a semiconductor substrate having a deep well of a first doping type; a device within a first portion of the deep well, the device including: a first doped semiconductor material coupled to a first contact, and having a second doping type opposite the first doping type; a second doped semiconductor material coupled to a second contact, having the second doping type, wherein the deep well couples the first doped semiconductor material to the second doped semiconductor material; a first back well within a second portion of the deep well, and having the first doping type; and a first resistive semiconductor material within the deep well and interposed between the first portion of the deep well and the second portion of the deep well. ### Claim 9 (depends on 8) The IC structure of claim 8, further comprising a trench isolation (TI) within the deep well and horizontally between the first back well and the device, wherein the first resistive semiconductor material is below a lower surface of the first back well and horizontally adjacent the TI. ### Claim 10 (depends on 8) The IC structure of claim 8, wherein the first resistive semiconductor material includes amorphous silicon (a-Si). ### Claim 11 (depends on 8) The IC structure of claim 8, further comprising: a second back well within a third portion of the deep well, wherein the first portion of the deep well is horizontally between the second portion and the third portion; and a second resistive semiconductor material within the deep well and interposed between the first portion of the deep well and the third portion of the deep well. ### Claim 12 (depends on 8) The IC structure of claim 8, wherein the device includes a transistor including: a source within the first doped semiconductor material, a drain within the second doped semiconductor material, and a gate over the first portion of the deep well, wherein the gate is horizontally between the first doped semiconductor material and the second doped semiconductor material. ### Claim 13 (depends on 8) The IC structure of claim 8, wherein the device includes an electrostatic discharge device (ESD) including: a first n-type semiconductor within the first doped semiconductor material, a second n-type semiconductor within the second doped semiconductor material, and a p-type semiconductor within the first portion of the deep well, wherein the p-type semiconductor is horizontally between the first n-type semiconductor and the second n-type semiconductor. ### Claim 14 (depends on 8) The IC structure of claim 8, further comprising an amorphous semiconductor (a-Si) layer within the semiconductor substrate, wherein the deep well is above the a-Si layer and a remainder of the semiconductor substrate is below the a-Si layer. ### Claim 15 An integrated circuit (IC) structure comprising: a semiconductor substrate having a deep well of a first doping type; a shallow well within the deep well, the shallow well having a second doping type opposite the first doping type; a device within a first portion of the deep well and within the shallow well, the device including: a first doped semiconductor material within the first portion of the deep well, coupled to a first contact, and having the second doping type, and a second doped semiconductor material within the shallow well, coupled to a second contact, having the first doping type, wherein the deep well couples the first doped semiconductor material to the second doped semiconductor material, a back well within a second portion of the deep well, and having the first doping type; and a resistive semiconductor material within the deep well and interposed between the first portion of the deep well and the second portion of the deep well. ### Claim 16 (depends on 15) The IC structure of claim 15, further comprising a trench isolation (TI) within the deep well and horizontally between the back well and the device, wherein the resistive semiconductor material is below a lower surface of the back well and horizontally adjacent the TI. ### Claim 17 (depends on 16) The IC structure of claim 16, wherein the first doped semiconductor material is adjacent the TI such that the TI is horizontally between the back well and the first doped semiconductor material. ### Claim 18 (depends on 15) The IC structure of claim 15, wherein the resistive semiconductor material includes amorphous silicon (a-Si). ### Claim 19 (depends on 15) The IC structure of claim 15, wherein the device includes a silicon controlled rectifier (SCR) including: an n-type semiconductor within the first doped semiconductor material, a p-type semiconductor within the second doped semiconductor material, and a gate semiconductor within the shallow well, and horizontally separated from the p-type semiconductor, wherein the first portion of the deep well is horizontally between the n-type semiconductor and the shallow well. ### Claim 20 (depends on 19) The IC structure of claim 19, further comprising a trench isolation (TI) within the shallow well, and horizontally between the p-type semiconductor and the gate semiconductor.