# US 12,191,296 B2 · Method of producing a multi-chip assembly

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- Number: US 12,191,296 B2
- Document ID: US12191296B2
- Status: Granted
- Kind: B2
- Application number: 17/520,924
- Filed: 2021-11-08
- Published: 2023-05-11
- Granted: 2025-01-07
- Earliest claimed: 2021-11-08
- Assignees: Infineon Technologies AG
- Applicants: Infineon Technologies AG
- Inventors: Ling Ma; Robert Haase; Timothy Henson
- Web page: https://patentgrep.com/patent/US12191296B2

## CPC

- H10P 72/74: {using temporarily an auxiliary support}
- H10W 90/00: Package configurations
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10P 58/00: Singulating wafers or substrates into multiple chips, i.e. dicing
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/7432: {used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10W 20/484: {Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/0198: {batch processes}
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 74/141: {the encapsulations being on at least the sidewalls of the semiconductor body}
- H10W 74/147: {the encapsulations being multilayered}
- H10W 90/10: Configurations of laterally-adjacent chips
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A multi-chip assembly includes: a first power transistor die having a source terminal facing a first direction and a drain terminal facing a second direction opposite the first direction; and a second power transistor die having a drain terminal facing the first direction, and a source terminal facing the second direction. A dielectric material occupies a gap between the first power transistor die and the second power transistor die, and secures the first power transistor die and the second power transistor die to one another. A metallization connects the source terminal of the first power transistor die to the drain terminal of the second power transistor die at a same side of the multi-chip assembly. The gap occupied by the dielectric material is less than 70 μm. Corresponding methods of producing multi-chip assemblies are also described.

## Claims

### Claim 1

A method of producing multi-chip assemblies, the method comprising:
processing a semiconductor wafer into a plurality of separated dies, the plurality of separated dies including a first group of separated dies and a second group of separated dies; and
via wafer-level processing:
reversing an orientation of the second group of separated dies such that the second group of separated dies have an opposite orientation as the first group of separated dies;
securing the separated dies of the first group and the second group to one another with a dielectric material;
electrically interconnecting groups of two or more adjacent ones of the separated dies from the first group and the second group; and
removing the dielectric material in a region between the groups of electrically interconnected dies to laterally separate the groups of electrically interconnected dies from one another.

### Claim 2 (depends on 1)

The method of claim 1, wherein as part of processing the semiconductor wafer, a first carrier is attached, via a first adhesive, to a first side of both the first group and the second group of separated dies, and wherein reversing the orientation of the second group of separated dies comprises:
attaching, via a second adhesive, a second carrier to a second side of both the first group and the second group of separated dies;
deactivating the first adhesive in a region corresponding to a location of the second group of separated dies, and the second adhesive in a region corresponding to a location of the first group of separated dies;
after the deactivating, separating the first carrier with the first group of separated dies from the second carrier with the second group of separated dies such that the second side of the first group of separated dies is no longer attached to the second carrier and the first side of the second group of separated dies is no longer attached to the first carrier;
after the separating, attaching a third carrier to the first side of the second group of separated dies which are attached to the second carrier at the second side;
after attaching the third carrier, removing the second carrier from the second side of the second group of separated dies;
flipping the third carrier such that the second side of the second group of separated dies faces a same direction as the first side of the first group of separated dies; and
attaching the second side of the second group of separated dies to the first carrier and the second side of the first group of separated dies to the third carrier.

### Claim 3 (depends on 2)

The method of claim 2, wherein securing the separated dies of the first group and the second group to one another with the dielectric material comprises:
removing the first carrier from the first side of the first group of separated dies and from the second side of the second group of separated dies; and
after removing the first carrier, covering the first group of separated dies and the second group of separated dies with the dielectric material.

### Claim 4 (depends on 3)

The method of claim 3, wherein electrically interconnecting groups of two or more adjacent ones of the separated dies from the first group and the second group comprises:
forming openings in the dielectric material that expose bond pads at the first side of the separated dies of the first group and at the second side of the separated dies of the second group;
depositing a metal or metal alloy over the dielectric material and in the openings; and
patterning the metal or metal alloy.

### Claim 5 (depends on 3)

The method of claim 3, wherein the dielectric material is an imide, an epoxy or BCB (benzocyclobutene).

### Claim 6 (depends on 1)

The method of claim 1, wherein processing the semiconductor wafer into the plurality of separated dies comprises:
laser or plasma etching trenches into a frontside of the semiconductor wafer;
thinning the semiconductor wafer at a backside of the semiconductor wafer; and
depositing a metallization layer on the thinned backside of the semiconductor wafer.

### Claim 7 (depends on 1)

The method of claim 1, wherein for each multi-chip assembly, a spacing between adjacent dies included in the multi-chip assembly is less than 70 μm.

### Claim 8 (depends on 7)

The method of claim 7, wherein for each multi-chip assembly, the spacing between adjacent dies included in the multi-chip assembly is in a range of 5 μm to 10 μm.

### Claim 9 (depends on 1)

The method of claim 1, wherein the plurality of separated dies are power transistor dies, wherein each multi-chip assembly includes one power transistor die from the first group and one power transistor die from the second group, and wherein for each multi-chip assembly, a source terminal of the power transistor die from the first group is electrically connected to a drain terminal of the power transistor die from the second group.

### Claim 10 (depends on 9)

The method of claim 9, wherein the power transistor dies of the first group and the power transistor dies of the second group have the same transistor cell configuration and the power transistor dies of the second group have a different shape and/or a different size than the power transistor dies of the first group.

### Claim 11 (depends on 9)

The method of claim 9, wherein the power transistor dies of the first group and the power transistor dies of the second group each have a simple polygon shape with more than four straight line segments.

### Claim 12 (depends on 9)

The method of claim 9, wherein the power transistor dies of the first group each have a simple polygon shape with four straight line segments, wherein the power transistor dies of the second group each have a polygon shape with four straight line segments and a hole, and wherein the hole in the power transistor dies of the second group is sized to receive one of the power transistor dies of the first group.