# US 12,191,295 B1 · Heterogeneous integration of radio frequency transistor chiplets having interconnections to host wafer circuits for optimizing operating conditions

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- Number: US 12,191,295 B1
- Document ID: US12191295B1
- Status: Granted
- Kind: B1
- Application number: 18/754,058
- Filed: 2024-06-25
- Granted: 2025-01-07
- Earliest claimed: 2024-06-25
- Assignees: PseudolithIC, Inc.
- Applicants: PseudolithIC, Inc.
- Inventors: James F. Buckwalter; Florian Herrault; Justin Kim; Michael Hodge; Daniel S. Green
- Web page: https://patentgrep.com/patent/US12191295B1

## CPC

- H10W 90/00: Package configurations
- H03K 17/56: by the use, as active elements, of semiconductor devices (using diodes H03K17/74)
- H10D 10/80: Heterojunction BJTs
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 74/014: {using batch processing}
- H10D 10/821: {Vertical heterojunction BJTs}
- H10D 84/401: {Combinations of FETs or IGBTs with BJTs}
- H10W 44/231: {Arrangements for applying bias}
- H10W 44/234: {Arrangements for impedance matching}
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An electronic assembly heterogeneously integrates radio-frequency (RF) transistor chiplets into a host wafer, and the chiplets have interconnections to host wafer circuits. The assembly has at least one RF transistor chiplet having a chiplet circuit including a high-electron-mobility transistor (HEMT) or a heterojunction bipolar transistor (HBT). The host wafer has at least one host wafer circuit for the purpose of producing bias conditions that optimize performance of the HEMT or HBT. The host wafer circuit includes first circuitry to provide a DC bias of the HEMT or HBT; or second circuitry configured to sense radio-frequency operating conditions of the HEMT or HBT. The electrical interconnects are between the chiplet and the wafer, and electrically connect the host wafer circuit to the chiplet circuit.

## Claims

### Claim 1

An electronic assembly for heterogeneous integration of radio frequency (RF) transistor chiplets having interconnections to host wafer circuits, the assembly comprising:
at least one RF transistor chiplet each having a chiplet circuit including a high-electron-mobility transistor (HEMT) or a heterojunction bipolar transistor (HBT);
a host wafer having at least one host wafer circuit for the purpose of producing bias conditions that optimize performance of the HEMT or HBT, the at least one host wafer circuit including one of:
first circuitry to provide a DC bias of the HEMT or HBT; or
second circuitry configured to sense radio-frequency operating conditions of the HEMT or HBT; and
electrical interconnects between the chiplet and the host wafer, wherein the electrical interconnects electrically connect the host wafer circuit to the chiplet circuit.

### Claim 2 (depends on 1)

The electronic assembly of claim 1, wherein the at least one chiplet includes at least two chiplets including a first chiplet having a first chiplet circuit having the high-electron-mobility transistor (HEMT) and a second chiplet having a second chiplet circuit having the heterojunction bipolar transistor (HBT).

### Claim 3 (depends on 1)

The electronic assembly of claim 1, wherein the at least one chiplet includes at least two chiplets including a first chiplet having the high-electron-mobility transistor (HEMT) and a second chiplet having another high-electron-mobility transistor (HEMT).

### Claim 4 (depends on 1)

The electronic assembly of claim 1, wherein the at least one chiplet includes at least two chiplets including a first chiplet having the heterojunction bipolar transistor (HBT) and a second chiplet having another heterojunction bipolar transistor (HBT).

### Claim 5 (depends on 1)

The electronic assembly of claim 1, wherein the at least one chiplet includes at least two chiplets each including one of: a chiplet circuit including at least one high-electron-mobility transistor (HEMT) and at least one heterojunction bipolar transistor (HBT), a chiplet circuit including at least two high-electron-mobility transistors (HEMTs), or a chiplet circuit including at least two heterojunction bipolar transistors (HBTs).

### Claim 6 (depends on 1)

The electronic assembly of claim 1, wherein the at least one chiplet includes at least two chiplets including a first chiplet formed from a first semiconductor material and a second chiplet is formed from a second semiconductor material, and the host wafer is formed from a third semiconductor material; and
wherein one of: the first and second semiconductor material are a different material than the third semiconductor material; or the first, second and third semiconductor materials are all different from each other.

### Claim 7 (depends on 1)

The electronic assembly of claim 1, wherein the first circuitry is configured to actuate DC biasing of the HEMT or HBT to optimize RF characteristics of the HEMT or HBT, and includes at least one CMOS transistor configured to at least one of:
provide biasing of a gate or base of the HEMT or HBT to optimize the ability of the HEMT or HBT to maintain maximum gain, output power, noise or efficiency; or
provide biasing of a drain or collector of the HEMT or HBT to moderate a voltage supply.

### Claim 8 (depends on 7)

The electronic assembly of claim 7, wherein providing biasing of the gate or base includes an NMOS transistor having a source electrically connected to the gate or base of the HEMT or HBT, and a drain electrically connected to a gate or base voltage supply for the HEMT or HBT to provide biasing of the gate or base of the HEMT or HBT; and
wherein providing biasing of the drain or collector includes a PMOS transistor having a source electrically connected to a drain or collector of the HEMT or HBT, and a drain electrically connected to a drain or collector voltage supply for the HEMT or HBT to provide biasing of a drain or collector of the HEMT or HBT to moderate a voltage supply on the host wafer.

### Claim 9 (depends on 1)

The electronic assembly of claim 1, wherein the second circuitry is configured to sense DC biases of the HEMT or HBT, and includes at least one a CMOS transistor configured to at least one of:
generate a voltage or current to a gate or base of the HEMT or HBT in response to RF power incident on the gate or base of the HEMT or HBT, or
generate a voltage or current to the drain or collector of the HEMT or HBT in response to the RF power incident on the drain or collector of the HEMT or HBT.

### Claim 10 (depends on 9)

The electronic assembly of claim 9, wherein generating a voltage or current to the gate or base includes an NMOS transistor having a source electrically connected to the gate or base of the HEMT or HBT, and a drain electrically connected to the gate or base voltage supply for the HEMT or HBT; and a feedback element including an operational amplifier having one input electrically connected to a gate or base reference voltage or current signal, a second input electrically connected to the gate or base of the HEMT or HBT and an output electrically connected to a gate of the NMOS transistor; and
wherein generating a voltage or current to the drain or collector includes a PMOS transistor having a source electrically connected to a drain or collector of the HEMT or HBT, and a drain electrically connected to a drain or collector voltage supply for the HEMT or HBT; and a feedback element including an operational amplifier having one input electrically connected to a drain or collector reference voltage or current signal, a second input electrically connected to the drain or collector of the HEMT or HBT and an output electrically connected to a gate of the PMOS transistor.

### Claim 11 (depends on 1)

The electronic assembly of claim 1, wherein the second circuitry includes a temperature sensor configured to sense the operating temperature of the HEMT or HBT, and to produce a reference voltage or current that is constant and proportional to the monitored temperature, wherein the temperature sensor includes:
a first P/N diode and a second P/N diode on the at least one chiplet and electrically coupled to the HEMT or HBT, the second diode having an electrical characteristic that is unequal to that of the first diode,
an operational amplifier,
a first feedback resistor between an output of the operational amplifier and a first input of the operational amplifier and the first diode, and
a second feedback resistor between the output of the operational amplifier and a second input of the operational amplifier and the second diode.

### Claim 12 (depends on 1)

The electronic assembly of claim 1, further comprising:
third circuitry configured to produce one of: analog or RF blocks in one of a transmitter or receiver chain that includes one of frequency multipliers, frequency mixers, phase shifters, signal attenuators, RF intermediate-frequency or baseband amplifiers.

### Claim 13 (depends on 1)

The electronic assembly of claim 1, further comprising:
a backside capping layer having a top surface and a back surface;
a back surface of the host wafer bonded to the top surface of the backside capping layer except for first and second cavities in the host wafer formed over first and second areas of the top surface of the backside capping layer, the first and a second cavities having first and a second side surfaces;
wherein the at least one chiplet includes at least two first chiplets each including a first chiplet circuit having the high-electron-mobility transistor (HEMT) and at least two second chiplets each including a second chiplet circuit having one of the heterojunction bipolar transistor (HBT);
wherein the HBT includes:
a first chiplet thickness, a first backside and a first frontside, the first backside of the first chiplet bonded directly to at least a first portion of a first area of the top surface of the backside capping layer, wherein the first portion has a first capping layer thickness of the backside capping layer;
wherein the HEMT includes:
a second chiplet thickness, a second backside and a second frontside, the second backside of the at least two second chiplets bonded directly to at least a second portion of a second area of the top surface of the backside capping layer, wherein the second portion has a second capping layer thickness of the backside capping layer; and
a lateral bonding material between side surfaces of the first and second chiplets and the first and a second side surfaces of the first and second cavities;
wherein the first chiplet thickness is greater than the second chiplet thickness;
wherein the first capping layer thickness of the backside capping layer is less than the second capping layer thickness of the backside capping layer; and
wherein the second capping layer thickness of the backside capping layer includes metal backfill plugs between the second backsides of the second at least two second chiplets and the first capping layer thickness of the backside capping layer.

### Claim 14 (depends on 1)

The electronic assembly of claim 1, wherein the host wafer is vertically diced along a perimeter of the host wafer around at least one chiplet to form chips each having the at least one chiplet, the interconnects and an area of the host wafer surrounding the at least one chiplet and having the at least one wafer circuit.

### Claim 15

An electronic assembly for heterogeneous integration of radio frequencies (RF) transistor chiplets having interconnections to host wafer circuits, the assembly comprising:
at least one RF transistor chiplet each having a chiplet circuit including a high-electron-mobility transistor (HEMT) or a heterojunction bipolar transistor (HBT);
a host wafer having at least one host wafer circuit for the purpose of optimizing operating conditions of the HEMT or HBT, the at least one host wafer circuit including one of:
first circuitry to provide a DC bias of the HEMT or HBT; or
second circuitry configured to sense radio-frequency operating conditions of the HEMT or HBT;
a lateral bonding material between side surfaces of the at least one RF transistor chiplet and side surfaces of cavities in the host wafer;
and
electrical interconnects between the at least one chiplet and the host wafer, wherein the electrical interconnects electrically connect the host wafer circuit to the chiplet circuit.

### Claim 16 (depends on 15)

The electronic assembly of claim 15, wherein the at least one chiplet includes at least two chiplets including a first chiplet having a first chiplet circuit having the high-electron-mobility transistor (HEMT) and a second chiplet having a second chiplet circuit having the heterojunction bipolar transistor (HBT).

### Claim 17 (depends on 15)

The electronic assembly of claim 15, wherein the at least one chiplet includes at least two chiplets each including one of: a chiplet circuit including at least one high-electron-mobility transistor (HEMT) and at least one heterojunction bipolar transistor (HBT), a chiplet circuit including at least two high-electron-mobility transistors (HEMTs), or a chiplet circuit including at least two heterojunction bipolar transistors (HBTs).

### Claim 18 (depends on 15)

The electronic assembly of claim 15, wherein the at least one chiplet includes a first chiplet and a second chiplet, wherein the first chiplet is formed from a first semiconductor material, the second chiplet is formed from a second semiconductor material, and the host wafer is formed from a third semiconductor material; and
wherein one of: the first and second semiconductor material are a different material than the third semiconductor material; or the first, second and third semiconductor materials are all different from each other.

### Claim 19 (depends on 15)

The electronic assembly of claim 15, wherein the second circuitry is for performing in extreme conditions including temperatures found in satellite electronics or cryogenic environments.

### Claim 20 (depends on 15)

The electronic assembly of claim 15, wherein the interconnects have a length in a range of between 10 and 80 microns, and a parasitic inductance of the interconnects is in a range of between 10 and 80 pico-Henrys (H).

### Claim 21 (depends on 15)

The electronic assembly of claim 15, wherein the HEMT is a high-electron-mobility field effect transistor utilizing a heterojunction of materials with different band gaps to enhance performance in high-frequency applications; and the HBT is a type of bipolar junction transistor (BJT) which uses differing semiconductor materials for emitter and base regions, creating a heterojunction to improve on the BJT by handling signals of very high frequencies, up to several hundred GHz.

### Claim 22 (depends on 15)

The electronic assembly of claim 15, wherein the host wafer includes at least one layer of silicon (Si); and wherein each chiplet includes at least two HEMTs or HBTs and the interconnects from the transistors to contact pads on a frontside surface of the chiplet; and wherein each chiplet is a pre-fabricated transistor chiplet.

### Claim 23

An electronic assembly comprising:
a plurality of RF transistor chiplets each having a chiplet circuit including a high-electron-mobility transistor (HEMT) or a heterojunction bipolar transistor (HBT);
a host wafer having at least one host wafer circuit for the purpose of tuning the operating bias conditions of the HEMT or HBT, the at least one host wafer circuit including:
first circuitry to provide a DC bias of the HEMT or HBT; and
second circuitry configured to sense radio-frequency operating conditions of the HEMT or HBT;
a lateral bonding material between side surfaces of the plurality of RF transistor chiplets and side surfaces of cavities in the host wafer; and
electrical interconnects between the chiplet and the host wafer, wherein the electrical interconnects electrically connect the host wafer circuit to the chiplet circuit.

### Claim 24 (depends on 23)

The electronic assembly of claim 23, wherein a first chiplet of the plurality of chiplets is formed from a first semiconductor material, a second chiplet of the plurality of chiplets is formed from a second semiconductor material, and the host wafer is formed from a third semiconductor material; and
wherein one of: the first and second semiconductor material are a different material than the third semiconductor material; or the first, second and third semiconductor materials are all different from each other.