# US 12,191,294 B2 · Package structure and method of forming the same

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- Number: US 12,191,294 B2
- Document ID: US12191294B2
- Status: Granted
- Kind: B2
- Application number: 18/334,390
- Filed: 2023-06-14
- Published: 2023-10-12
- Granted: 2025-01-07
- Earliest claimed: 2021-08-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Po-Yao Lin; Shu-Shen Yeh; Chin-Hua Wang; Yu-Sheng Lin; Shin-Puu Jeng
- Web page: https://patentgrep.com/patent/US12191294B2

## CPC

- H10W 90/00: Package configurations
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/685: comprising multiple insulating layers
- H10W 74/01: Manufacture or treatment
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10W 40/10: Arrangements for heating
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/698: Semiconductor materials that are electrically insulating, e.g. undoped silicon
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Provided are a package structure and a method of forming the same. The package structure includes a first tier, a second tier, and a third tier. The first tier includes an interposer. The second tier is disposed on the first tier and includes a bottom die. The third tier is disposed on the second tier and includes a plurality of first dies and at least one second die. The at least one second die is disposed between the plurality of first dies. The plurality of first dies are electrically connected to the bottom die by a plurality of first connectors to form a signal path, the plurality of first dies are electrically connected to the interposer by a plurality of second connectors to form a power path, and the plurality of first connectors are closer to the at least one second die than the plurality of second connectors.

## Claims

### Claim 1

A package structure, comprising:
an interposer;
a bottom die disposed on the interposer, wherein the interposer has a width greater than a width of the bottom die so that a sidewall of the interposer is laterally offset outward from a sidewall of the bottom die; and
at least one first die disposed on the bottom die and across the sidewall of the bottom die,
wherein the at least one first die is electrically connected to the bottom die by a signal transmission region, the at least one first die is electrically connected to the interposer by a power transmission region, and the signal transmission region has a vertical height less than a vertical height of the power transmission region.

### Claim 2 (depends on 1)

The package structure of claim 1, further comprising:
a first tier comprising the interposer;
a second tier disposed on the first tier and comprising the bottom die; and
a third tier disposed on the second tier, wherein the third tier comprises a plurality of first dies and at least one second die, the at least one second die is disposed between the plurality of first dies, and the plurality of first dies are different from the at least one second die.

### Claim 3 (depends on 2)

The package structure of claim 2, wherein the bottom die is completely overlapped with the at least one second die, and the bottom die is partially overlapped with the plurality of first dies.

### Claim 4 (depends on 2)

The package structure of claim 2, wherein the sidewall of the bottom die is located between an outer sidewall and an inner sidewall of the plurality of first dies, and the outer sidewall of the plurality of first dies is closer to the sidewall of the bottom die than the inner sidewall of the plurality of first dies.

### Claim 5 (depends on 2)

The package structure of claim 2, wherein the second tier further comprises:
an encapsulant laterally encapsulating the bottom die; and
a plurality of through insulating vias (TIVs) embedded in the encapsulant to surround the bottom die.

### Claim 6 (depends on 5)

The package structure of claim 5, wherein the signal transmission region comprises a plurality of first connectors disposed between the plurality of first dies and the bottom die, and the power transmission region comprises a plurality of second connectors and the plurality of TIVs disposed between the plurality of first dies and the interposer.

### Claim 7 (depends on 6)

The package structure of claim 6, wherein the plurality of first connectors has a pattern density greater than a pattern density of the plurality of second connectors.

### Claim 8 (depends on 6)

The package structure of claim 6, wherein the bottom die comprises a plurality of through substrate vias (TSVs) to electrically connect the plurality of first connectors.

### Claim 9 (depends on 1)

The package structure of claim 1, wherein the interposer comprises a redistribution layer (RDL) structure.

### Claim 10

A method of forming a package structure, comprising:
forming a first tier comprising an organic interposer on a carrier;
forming first connectors on the organic interposer;
forming a second tier including a bottom die on the first tier, wherein the bottom die is electrically connected with the organic interposer through the first connectors;
forming second connectors, third connectors and fourth connectors on the second tier; and forming a third tier including first dies and at least one second die on the second tier, wherein the second connectors are disposed between the first dies and the bottom die, the third connectors are disposed between the first dies and the organic interposer, and the fourth connectors are disposed between the at least one second die and the bottom die,
wherein the first dies are electrically connected to the bottom die by the second connectors to form a signal path, the first dies are electrically connected to the organic interposer by the third connectors to form a power path, and the second connectors are located closer to the at least one second die than the third connectors.

### Claim 11 (depends on 10)

The method of claim 10, further comprising forming through insulating vias (TIVs) on the organic interposer before forming the first connectors.

### Claim 12 (depends on 11)

The method of claim 11, wherein forming a second tier including a bottom die on the first tier comprises bonding the bottom die onto the organic interposer, and forming a first encapsulant covering the bottom die and the TIVs.

### Claim 13 (depends on 12)

The method of claim 12, wherein the bottom die comprises a substrate and through substrate vias (TSVs) embedded in the substrate, and the method further comprises performing a planarization process to partially remove the first encapsulant and partially remove the substrate to expose the TSVs.

### Claim 14 (depends on 10)

The method of claim 10, wherein forming a third tier including first dies and at least one second die on the second tier further comprises:
forming a second encapsulant to laterally encapsulate the first dies and the at least one second die, wherein the second encapsulant exposes a backside of the plurality of first dies and a backside of the at least one second die; and
attaching a heat sink on the backside of the plurality of first dies and the backside of the at least one second die.

### Claim 15

A package structure, comprising:
a first tier;
a second tier disposed on the first tier; and
a third tier disposed on the second tier,
wherein the third tier is electrically connected to the second tier by a signal transmission region, the third tier is electrically connected to the first tier by a power transmission region across the second tier, and the signal transmission region has a pattern density greater than a pattern density of the power transmission region.

### Claim 16 (depends on 15)

The package structure of claim 15, wherein:
the first tier comprising an interposer;
the second tier comprising a bottom die; and
the third tier comprises a plurality of first dies and at least one second die, the at least one second die is disposed between the plurality of first dies, the plurality of first dies are electrically connected to the bottom die by the signal transmission region, and the plurality of first dies are electrically connected to the interposer by the power transmission region across the bottom die.

### Claim 17 (depends on 16)

The package structure of claim 16, wherein the second tier further comprises:
an encapsulant laterally encapsulating the bottom die; and
a plurality of through insulating vias (TIVs) embedded in the encapsulant to surround the bottom die.

### Claim 18 (depends on 17)

The package structure of claim 17, wherein the signal transmission region comprises a plurality of first connectors disposed between the plurality of first dies and the bottom die, and the power transmission region comprises a plurality of second connectors and the plurality of TIVs disposed between the plurality of first dies and the interposer.

### Claim 19 (depends on 16)

The package structure of claim 16, wherein the bottom die is a system on chip (SoC) die.

### Claim 20 (depends on 16)

The package structure of claim 16, wherein the plurality of first dies comprise high bandwidth memory (HBM) dies, and the at least one second die comprises a static random access memory (SRAM) die, a system on chip (SoC) die, a dummy die, a chip scale package (CSP), or a combination thereof.