# US 12,191,290 B2 · Semiconductor package with recessed molding region disposed below housing and above semiconductor chip > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,191,290 B2 - Document ID: US12191290B2 - Status: Granted - Kind: B2 - Application number: 17/671,742 - Filed: 2022-02-15 - Published: 2022-12-08 - Granted: 2025-01-07 - Earliest claimed: 2021-06-03 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: In-Jae Lee - Web page: https://patentgrep.com/patent/US12191290B2 ## CPC - H10W 76/12: characterised by their shape - H10W 90/00: Package configurations - H01R 13/665: {with built-in electronic circuit (H01R13/70, H01R13/719 take precedence)} - H10W 72/0198: {batch processes} - H10W 74/014: {using batch processing} - H10W 74/016: {using moulds} - H10W 74/114: {by a substrate and the encapsulations} - H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation} - H10W 90/288: {characterised by arrangements for thermal management of the stacked chips} - H01R 24/62: Sliding engagements with one side only, e.g. modular jack coupling devices - H10W 72/01515: {Forming coatings} - H10W 72/073: {of die-attach connectors} - H10W 72/07327: {involving guiding structures, e.g. spacers or supporting members} - H10W 72/07354: {changes in dispositions} - H10W 72/075: {of bond wires} - H10W 72/347: {Dispositions of multiple die-attach connectors} - H10W 72/865: {Die-attach connectors and bond wires} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/10: characterised by their shape or disposition - H10W 76/47: Solid or gel fillings - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/732: {between stacked chips} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/752: {between stacked chips} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H01R: ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS ## Abstract A semiconductor package includes a package substrate, a semiconductor chip on the package substrate, the semiconductor chip including a logic chip and a memory stack structure on the logic chip, a connector and a connector terminal below the package substrate, a molding layer that covers the semiconductor chip, the molding layer having a recess region on a top surface of the molding layer, a housing that covers the molding layer, and an air gap on the semiconductor chip, the air gap being defined by the housing and the recess region of the molding layer, and the molding layer separating the air gap from the memory stack structure of the semiconductor chip. ## Claims ### Claim 1 A semiconductor package, comprising: a package substrate; a semiconductor chip on the package substrate, the semiconductor chip including a logic chip and a memory stack structure on the logic chip; a connector and a connector terminal below the package substrate; a molding layer that covers the semiconductor chip, the molding layer having a recess region on a top surface of the molding layer; a housing that covers the molding layer; and an air gap on the semiconductor chip, the air gap being defined by the housing and the recess region of the molding layer, and the molding layer separating the air gap from the memory stack structure of the semiconductor chip, wherein a portion of the molding layer is disposed between a top surface of the semiconductor chip and a bottom surface of the recess region. ### Claim 2 (depends on 1) The semiconductor package as claimed in claim 1, wherein a width of the air gap gradually increases in a direction perpendicular to a top surface of the package substrate. ### Claim 3 (depends on 1) The semiconductor package as claimed in claim 1, wherein the housing includes: a first part on the top surface of the molding layer, the air gap being defined by the molding layer and the first part; second part below the package substrate; and a third part that connects the first part and the second part to each other. ### Claim 4 (depends on 3) The semiconductor package as claimed in claim 3, further comprising an opening defined by a bottom surface of the package substrate, the second part, and the third part. ### Claim 5 (depends on 1) The semiconductor package as claimed in claim 1, wherein the air gap vertically overlaps the semiconductor chip. ### Claim 6 (depends on 1) The semiconductor package as claimed in claim 1, wherein a portion of the air gap is offset from the semiconductor chip. ### Claim 7 (depends on 1) The semiconductor package as claimed in claim 1, wherein a width at the bottom surface of the recess region is in a range of about 1.2 mm to about 1.5 mm. ### Claim 8 (depends on 1) The semiconductor package as claimed in claim 1, wherein a thickness of the air gap is in a range of about 0.2 mm to about 0.6 mm. ### Claim 9 (depends on 1) The semiconductor package as claimed in claim 1, wherein a shortest distance between the memory stack structure and the bottom surface of the recess region is in a range of about 0.1 mm to about 1.2 mm. ### Claim 10 (depends on 1) The semiconductor package as claimed in claim 1, wherein the semiconductor chip further includes a dummy chip below the memory stack structure, the dummy chip being spaced apart from the logic chip. ### Claim 11 A semiconductor package, comprising: a package substrate; a semiconductor chip on the package substrate, the semiconductor chip including a logic chip and a memory stack structure on the logic chip; a connector below the package substrate; a molding layer that covers the semiconductor chip, the molding layer having a recess region on a top surface of the molding layer; a housing that covers the molding layer, the housing including a first part on the top surface of the molding layer, a second part below the package substrate, and a third part that connects the first part and the second part to each other; and an air gap defined by the first part of the housing and the recess region of the molding layer, the air gap vertically overlapping the semiconductor chip, wherein a portion of the molding layer is disposed between a top surface of the semiconductor chip and a bottom surface of the recess region. ### Claim 12 (depends on 11) The semiconductor package as claimed in claim 11, wherein a thickness of the air gap is in a range of about 0.2 mm to about 0.6 mm. ### Claim 13 (depends on 11) The semiconductor package as claimed in claim 11, wherein the molding layer separates the memory stack structure from the air gap. ### Claim 14 (depends on 11) The semiconductor package as claimed in claim 11, wherein the semiconductor chip further includes a dummy chip below the memory stack structure, the dummy chip being spaced apart from the logic chip. ### Claim 15 (depends on 11) The semiconductor package as claimed in claim 11, further comprising a passive element on the package substrate, the passive element being spaced apart from the semiconductor chip. ### Claim 16 A semiconductor package, comprising: a package substrate; a semiconductor chip on the package substrate, the semiconductor chip including a logic chip and a memory stack structure on the logic chip; a passive element on the package substrate and spaced apart from the semiconductor chip; a connector and a connector terminal below the package substrate; a molding layer that covers the semiconductor chip and the passive element, the molding layer having a recess region on a top surface of the molding layer; a housing that covers the molding layer, the housing including a first part on the top surface of the molding layer, a second part below the package substrate, and a third part that connects the first part and the second part to each other; an opening defined by a bottom surface of the package substrate, the second part, and the third part; and an air gap defined by the first part of the housing and the recess region of the molding layer, the molding layer separating the memory stack structure from the air gap, wherein a portion of the molding layer is disposed between a top surface of the semiconductor chip and a bottom surface of the recess region. ### Claim 17 (depends on 16) The semiconductor package as claimed in claim 16, wherein: a thickness of the air gap is in a range of about 0.2 mm to about 0.6 mm, and a width at the bottom surface of the recess region is in a range of about 1.2 mm to about 1.5 mm. ### Claim 18 (depends on 16) The semiconductor package as claimed in claim 16, wherein the air gap vertically overlaps the semiconductor chip. ### Claim 19 (depends on 16) The semiconductor package as claimed in claim 16, wherein a width of the air gap gradually increases in a direction perpendicular to a top surface of the package substrate. ### Claim 20 (depends on 16) The semiconductor package as claimed in claim 16, wherein a shortest distance between the memory stack structure and the bottom surface of the recess region is in a range of about 0.1 mm to about 1.2 mm.