# US 12,191,289 B2 · Semiconductor device

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- Number: US 12,191,289 B2
- Document ID: US12191289B2
- Status: Granted
- Kind: B2
- Application number: 18/464,169
- Filed: 2023-09-08
- Published: 2023-12-28
- Granted: 2025-01-07
- Earliest claimed: 2018-06-20
- Assignees: Rohm Co., Ltd.
- Applicants: Rohm Co., Ltd.
- Inventors: Yuji Ishimatsu; Ryuichi Furutani
- Web page: https://patentgrep.com/patent/US12191289B2

## CPC

- H10W 90/00: Package configurations
- H10W 20/497: {Inductive arrangements or effects of, or between, wiring layers}
- H10W 40/778: {in encapsulations}
- H10W 70/411: {Chip-supporting parts, e.g. die pads}
- H10W 70/413: {Insulating or insulated substrates serving as die pads (H10W70/468 takes precedence)}
- H10W 70/461: {specially adapted for cooling}
- H10W 70/468: {Circuit boards}
- H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 90/811: {Multiple chips on leadframes}
- H10W 70/421: {Shapes or dispositions}
- H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)}
- H10W 70/427: {Bent parts}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/073: {of die-attach connectors}
- H10W 72/075: {of bond wires}
- H10W 72/07552: {changes in structures or sizes}
- H10W 72/527: {Multiple bond wires having different sizes}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/5366: {the bond wires having kinks}
- H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements}
- H10W 72/5473: {multiple bond wires connected to a common bond pad}
- H10W 72/5475: {multiple bond wires connected to common bond pads at both ends of the wires}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/753: {between laterally-adjacent chips}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device A1 includes a substrate 3, a conductive section 5 formed on the substrate 3 and including a conductive material, a lead 1A located on the substrate 3, a semiconductor chip 4A located on the lead 1A, a control chip 4G located on the substrate 3 and electrically connected to the conductive section 5 and the semiconductor chip 4A for controlling an operation of the semiconductor chip 4A, and a resin 7 covering the semiconductor chip 4A, the control chip 4G, at least a part of the substrate 3 and a part of the lead 1A. This configuration contributes to achieving a higher level of integration of the semiconductor device.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate that is insulating and includes a substrate main surface and a substrate back surface;
a plurality of wiring patterns formed on a substrate main surface of the substrate;
a plurality of semiconductor switching chips that include a first electrode and a control electrode formed on a chip main surface side and a second electrode formed on a chip back surface and perform switching operation between the first electrode and the second electrode in response to a signal input to the control electrode;
a control chip that generates a signal to be input to the control electrode;
a plurality of first leads to be electrically connected to the first electrode or the second electrode;
a plurality of second leads to be electrically connected to the control chip;
an encapsulating resin covering at least a part of the plurality of first leads and the plurality of second leads, the substrate, the plurality of wiring patterns, and the plurality of semiconductor switching chips; and
a conductive bonding material extending outwardly from an outer periphery of the control chip, in a direction parallel to the substrate main surface,
wherein at least a part of the plurality of wiring patterns is arranged in a middle of a path connecting the control electrode and the control chip as an independent wiring pattern.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein a minimum separation between the plurality of wiring patterns is smaller than a minimum separation between the plurality of first leads.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the plurality of first leads are exposed only from one lateral side of the encapsulating resin.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein a separation between two adjacent ones of the plurality of first leads is larger than a separation between two adjacent ones of the plurality of second leads.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the encapsulating resin has a recess formed at a part of the encapsulating resin where the plurality of the plurality of are exposed from the encapsulating resin.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein each of the semiconductor switching chips is a metal-oxide-semiconductor field-effect transistor (MOSFET) formed on a silicon carbide (SiC) substrate, and
the first electrode is a source electrode, the second electrode is a drain electrode, and the control electrode is a gate electrode.

### Claim 7 (depends on 6)

The semiconductor device according to claim 6, wherein the gate electrode of the MOSFET has a trench structure.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, wherein heights of the semiconductor switching chips and a height of the control chip are different from each other when seen along a direction orthogonal to the substrate main surface.

### Claim 9 (depends on 8)

The semiconductor device according to claim 8, wherein a thickness of the wiring patterns is smaller than a thickness of the first leads.

### Claim 10 (depends on 1)

The semiconductor device according to claim 1, wherein the substrate is made of at least one ceramic selected from alumina (Al2O3), silicon nitride (SiN), aluminum nitride (AlN), and zirconia-containing alumina.

### Claim 11 (depends on 1)

The semiconductor device according to claim 1, wherein the semiconductor chips comprise low-voltage side switching elements and high-voltage side switching elements serially connected between a first power source and a second power source.

### Claim 12 (depends on 1)

The semiconductor device according to claim 1, wherein the control chip includes a first integrated circuit element to control an operation of the high-voltage side switching elements, and a second integrated circuit element to control an operation of the low-voltage side switching elements.

### Claim 13 (depends on 12)

The semiconductor device according to claim 12, further comprising a plurality of boot diodes electrically connected to the first integrated circuit element.

### Claim 14 (depends on 1)

The semiconductor device according to claim 1, wherein among the plurality of first leads, an external first lead covered by the encapsulating resin includes a part that faces inwards.

### Claim 15 (depends on 1)

The semiconductor device according to claim 1, wherein each of the semiconductor switching chips is a SiC-MOSFET or an IGBT including electrodes on a front surface and a back surface, or a GaN including electrodes on a front surface.

### Claim 16 (depends on 1)

The semiconductor device according to claim 1, wherein a first voltage level of an electrical signal applied to the second lead is lower than a second voltage level for driving the control chip.

### Claim 17 (depends on 1)

The semiconductor device according to claim 1, wherein heights of the plurality of semiconductor switching chips and heights of the control chips are different with respect to a direction orthogonal to the substrate main surface.