# US 12,191,288 B2 · Integrated voltage regulator (IVR) package including inductor and capacitor and IVR system package including the IVR package

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- Number: US 12,191,288 B2
- Document ID: US12191288B2
- Status: Granted
- Kind: B2
- Application number: 17/947,113
- Filed: 2022-09-17
- Published: 2023-08-10
- Granted: 2025-01-07
- Earliest claimed: 2022-02-09
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Sangnam Jeong; Yunhee Lee
- Web page: https://patentgrep.com/patent/US12191288B2

## CPC

- H10W 72/00: Interconnections or connectors in packages
- H10W 90/00: Package configurations
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 70/685: comprising multiple insulating layers
- H10W 70/692: Ceramics or glasses
- H10W 72/07252: {changes in structures or sizes}
- H10W 72/07254: {changes in dispositions}
- H10W 72/07554: {changes in dispositions}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/865: {Die-attach connectors and bond wires}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Provided are an integrated voltage regulator (IVR) package with a minimized size including one or more inductors and one or more capacitors together with an IVR chip and improving characteristics of a voltage regulator (VR), and an IVR system package including the IVR package. The IVR package includes a package substrate, a stacked structure mounted on the package substrate and having a stack structure in which a passive device chip including one or more capacitors and an IVR chip including a voltage regulator are stacked, and an intermediate substrate disposed on the package substrate in a structure surrounding the stacked structure, the intermediate substrate including vias therein. The one or more inductors are included in the stacked structure or the intermediate substrate.

## Claims

### Claim 1

An integrated voltage regulator (IVR) package comprising:
a package substrate;
a stacked structure mounted on the package substrate and having a stack structure in which a passive device chip comprising one or more capacitors and an IVR chip including a voltage regulator are stacked; and
an intermediate substrate disposed on the package substrate and having a structure surrounding the stacked structure, the intermediate substrate including vias therein,
wherein one or more inductors are included in the intermediate substrate.

### Claim 2 (depends on 1)

The IVR package of claim 1, wherein the stacked structure further includes a lower chip, and
wherein the stacked structure has a structure in which the lower chip and the passive device chip are positioned at a lower portion of the stacked structure and the IVR chip is disposed on the lower chip and the passive device chip.

### Claim 3 (depends on 2)

The IVR package of claim 2, wherein the one or more inductors are formed in the intermediate substrate by using the vias.

### Claim 4 (depends on 2)

The IVR package of claim 2, wherein the IVR chip comprises logic devices, and
wherein the lower chip comprises a logic chip, a memory chip, or a dummy chip.

### Claim 5 (depends on 1)

The IVR package of claim 1, wherein the stacked structure has a structure in which the passive device chip is positioned at a lower portion of the stacked structure and the IVR chip is disposed on the passive device chip.

### Claim 6 (depends on 5)

The IVR package of claim 5, wherein the one or more inductors are further formed in the passive device chip.

### Claim 7 (depends on 1)

The IVR package of claim 1, wherein the stacked structure has a structure in which the IVR chip is positioned at a lower portion of the stacked structure and the passive device chip is disposed on the IVR chip, and
wherein the IVR chip comprises through electrodes.

### Claim 8 (depends on 1)

The IVR package of claim 1, wherein the package substrate is wafer-based or panel-based, and
wherein the package substrate has a fan-out wafer level package (FOWLP) structure or a fan-out panel level package (FOPLP) structure according to a type of the package substrate.

### Claim 9

An integrated voltage regulator (IVR) system package comprising:
an IVR package; and
a memory package including a memory chip and stacked on the IVR package,
wherein the IVR package comprises:
a lower package substrate;
a stacked structure mounted on the lower package substrate and having a stack structure in which a passive device chip including one or more capacitors and an IVR chip including a voltage regulator are stacked; and
an intermediate substrate disposed on the lower package substrate in a structure surrounding the stacked structure, and including vias therein, and
wherein one or more inductors are included in the stacked structure or the intermediate substrate.

### Claim 10 (depends on 9)

The IVR system package of claim 9, wherein the stacked structure further comprises a lower chip,
wherein the stacked structure has a structure in which the lower chip and the passive device chip are positioned at a lower portion of the stacked structure and the IVR chip is disposed on the lower chip and the passive device chip, and
wherein the one or more inductors are formed in the intermediate substrate by using the vias.

### Claim 11 (depends on 10)

The IVR system package of claim 10, wherein the IVR chip includes logic circuits, and
wherein the lower chip comprises a logic chip, a memory chip, or a dummy chip.

### Claim 12 (depends on 9)

The IVR system package of claim 9, wherein the stacked structure has a structure in which the passive device chip is positioned at a lower portion of the stacked structure and the IVR chip is disposed on the passive device chip, and
wherein the one or more inductors are formed in the intermediate substrate by using the vias or are formed in the passive device chip.

### Claim 13 (depends on 9)

The IVR system package of claim 9, wherein the IVR package further comprises a first sealing material configured to fill a space between the stacked structure and the intermediate substrate and seal the stacked structure.

### Claim 14 (depends on 9)

The IVR system package of claim 9, wherein the memory package comprises an upper package substrate, the memory chip mounted on the upper package substrate, and a second sealing material configured to seal the memory chip.

### Claim 15 (depends on 14)

The IVR system package of claim 14, wherein the memory package further comprises a connection terminal on a bottom surface of the upper package substrate, and
wherein the memory package is mounted on the intermediate substrate through the connection terminal.

### Claim 16 (depends on 9)

The IVR system package of claim 9, wherein the lower package substrate is wafer-based or panel-based, and
wherein the lower package substrate has a fan-out wafer level package (FOWLP) structure or a fan-out panel level package (FOPLP) structure according to a type of the lower package substrate.

### Claim 17

A 3-dimensional (3D) package having a package on package (POP) structure, the 3D package comprising:
a lower package substrate;
a passive device chip mounted on the lower package substrate and comprising one or more capacitors;
a lower chip mounted on the lower package substrate and disposed adjacent to the passive device chip;
an integrated voltage regulator (IVR) chip disposed commonly over the passive device chip and the lower chip, and including a voltage regulator;
an intermediate substrate disposed on the lower package substrate in a structure surrounding the passive device chip, the lower chip, and the IVR chip, the intermediate substrate including vias therein;
an inner sealing material configured to fill a space between the passive device chip, the lower chip, and the IVR chip and the intermediate substrate and sealing the passive device chip, the lower chip, and the IVR chip; and
a memory package mounted on the intermediate substrate, and including a memory chip,
wherein one or more inductors are arranged in the intermediate substrate by using the vias.

### Claim 18 (depends on 17)

The 3D package of claim 17, wherein the IVR chip includes logic circuits, wherein the passive device chip comprises an integrated stacked capacitor (ISC) chip, and wherein the lower chip comprises a logic chip, a memory chip, or a dummy chip.

### Claim 19 (depends on 17)

The 3D package of claim 17, wherein the memory package comprises an upper package substrate, at least one memory chip mounted on the upper package substrate, and an upper sealing material configured to seal the at least one memory chip, and
wherein the memory package is mounted on the intermediate substrate through a connection terminal on a bottom surface of the upper package substrate.

### Claim 20 (depends on 17)

The 3D package of claim 17, wherein the lower package substrate is wafer-based or panel-based, and
wherein the lower package substrate has a fan-out wafer level package (FOWLP) structure or a fan-out panel level package (FOPLP) structure according to a type of the lower package substrate.