# US 12,191,287 B2 · Package structure

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- Number: US 12,191,287 B2
- Document ID: US12191287B2
- Status: Granted
- Kind: B2
- Application number: 18/474,168
- Filed: 2023-09-25
- Published: 2024-01-11
- Granted: 2025-01-07
- Earliest claimed: 2016-11-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Jing-Cheng Lin; Po-Hao Tsai
- Web page: https://patentgrep.com/patent/US12191287B2

## CPC

- H10W 90/00: Package configurations
- H10P 14/6542: {by using coherent radiation, e.g. using a laser}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/019: {of bond pads}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/90: Bond pads, in general
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics}
- H10W 40/73: for cooling by change of state
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/095: {of vias therein}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 72/0198: {batch processes}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/07352: {changes in structures or sizes}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/321: {Structures or relative sizes of die-attach connectors}
- H10W 72/354: {comprising polymers}
- H10W 72/5473: {multiple bond wires connected to a common bond pad}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/016: {using moulds}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 80/743: {having disposition changed during the connecting}
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/721: {of bump connectors}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A package structure includes a first semiconductor package and a second semiconductor package over the first semiconductor package. The first semiconductor package includes a dielectric structure, a semiconductor device on the dielectric structure, under bump metallization (UBM) structures in the dielectric structure. The USB structures each include a first region and a second region surrounded by the first region. The first region has more metal layers than the second region. The bumps are respectively on the second regions of the UBM structures.

## Claims

### Claim 1

A package structure comprising:
a first semiconductor package comprising:
a dielectric structure;
a semiconductor device on the dielectric structure;
a plurality of under bump metallization (UBM) structures in the dielectric structure, each of the plurality of UBM structures comprising a ledge and a cup-shaped portion, the ledge extending from an edge of the cup-shaped portion, wherein the ledge of each of the plurality of UBM structures comprises a seed layer, and the cup-shaped portion of each of the plurality of UBM structures is free of the seed layer; and
a plurality of bumps respectively on the cup-shaped portions of the UBM structures, wherein one of the plurality of bumps is in direct contact with the seed layer of the ledge of one of the plurality of UBM structures; and
a second semiconductor package over the first semiconductor package.

### Claim 2 (depends on 1)

The package structure of claim 1, wherein the ledge of each of the plurality of UBM structures further comprises a conductive feature over the seed layer, and the conductive feature is thicker than the seed layer.

### Claim 3 (depends on 2)

The package structure of claim 2, wherein the cup-shaped portion of each of the plurality of UBM structures comprises the conductive feature.

### Claim 4 (depends on 1)

The package structure of claim 1, wherein the first semiconductor package further comprises a molding compound encapsulating the semiconductor device.

### Claim 5 (depends on 4)

The package structure of claim 4, wherein the first semiconductor package further comprises a conductive through via extending through the molding compound.

### Claim 6 (depends on 5)

The package structure of claim 5, wherein the conductive through via comprises a seed layer over the dielectric structure, and a conductive feature over the seed layer of the conductive through via.

### Claim 7 (depends on 5)

The package structure of claim 5, further comprising:
an electrical connector over the conductive through via and below the second semiconductor package; and
an underfill material encapsulating the electrical connector.

### Claim 8 (depends on 7)

The package structure of claim 7, wherein the underfill material is in contact with a top surface of the semiconductor device, a top surface of the molding compound, and a bottom surface of the second semiconductor package.

### Claim 9

A package structure comprising:
a first semiconductor package comprising:
a dielectric structure;
a semiconductor device on the dielectric structure;
an UBM structure in the dielectric structure; and
an redistribution line in the dielectric structure, wherein from a cross-sectional view, the redistribution line has a tapered portion in direct contact with the UBM structure, the tapered portion of the redistribution line has a width increasing as a distance from the UBM structure increases; and
a second semiconductor package over the first semiconductor package.

### Claim 10 (depends on 9)

The package structure of claim 9, wherein from the cross-sectional view, the UBM structure has a width increasing as a distance from the tapered portion of the redistribution line increases.

### Claim 11 (depends on 9)

The package structure of claim 9, wherein the first semiconductor package further comprises a contact pad extending from a top surface of the dielectric structure into the dielectric structure, and from the cross-sectional view, the contact pad has a width decreasing as a distance from the top surface of the dielectric structure increases.

### Claim 12 (depends on 11)

The package structure of claim 11, wherein the first semiconductor package further comprises a molding compound surrounding the semiconductor device, and a through via extending through the molding compound to the contact pad.

### Claim 13 (depends on 12)

The package structure of claim 12, wherein from the cross-sectional view, the contact pad has a width variation greater than a width variation of the through via.

### Claim 14 (depends on 9)

The package structure of claim 9, wherein the first semiconductor package further comprises an underfill layer between the semiconductor device and the dielectric structure, and the underfill layer has a width decreasing as a distance from the dielectric structure increases.

### Claim 15

A package structure comprising:
a first semiconductor package comprising a dielectric structure, a semiconductor device over the dielectric structure, a first molding compound encapsulating the semiconductor device, and a plurality of through vias extending through the first molding compound;
a plurality of electrical connectors respectively over the plurality of through vias;
a second semiconductor package over the plurality of electrical connectors; and
an underfill material encapsulating the second semiconductor package and the plurality of electrical connectors, wherein the underfill material is in contact with a top surface of the first molding compound and a top surface of the semiconductor device.

### Claim 16 (depends on 15)

The package structure of claim 15, wherein the underfill material is further in contact with a bottom surface of the second semiconductor package.

### Claim 17 (depends on 15)

The package structure of claim 15, wherein the underfill material is spaced apart from the plurality of through vias.

### Claim 18 (depends on 15)

The package structure of claim 15, wherein the second semiconductor package comprises one or more dies encapsulated in a second molding compound.

### Claim 19 (depends on 1)

The package structure of claim 1, wherein in a cross-sectional view, the seed layer of one of the plurality of UBM structures has a vertical dimension and a lateral dimension greater than the vertical dimension.

### Claim 20 (depends on 1)

The package structure of claim 1, wherein the seed layer of one of the plurality of UBM structures has a first side surface and a second side surface relative to the first side surface.