# US 12,191,284 B2 · Thermally efficient semiconductor device assemblies including interposers carrying a subset of the external contacts of the assembly, and methods of making the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,191,284 B2 - Document ID: US12191284B2 - Status: Granted - Kind: B2 - Application number: 18/231,192 - Filed: 2023-08-07 - Published: 2023-11-23 - Granted: 2025-01-07 - Earliest claimed: 2020-12-31 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Pezhman Monadgemi - Web page: https://patentgrep.com/patent/US12191284B2 ## CPC - H10W 90/00: Package configurations - H10W 70/40: Leadframes - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/072: {of bump connectors} - H10W 72/073: {of die-attach connectors} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/59: Bond pads specially adapted therefor - H10W 72/877: {Bump connectors and die-attach connectors} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 72/9413: {on encapsulations} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL - H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape - H10W 90/288: {characterised by arrangements for thermal management of the stacked chips} - H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips} - H10W 90/721: {of bump connectors} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/732: {between stacked chips} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/752: {between stacked chips} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/796: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device assembly comprises a substrate including internal contacts on a first side and first external contacts on a second side. The assembly further comprises one or more first dies disposed over the first side and electrically coupled to the internal contacts, and a interposer having a length and a width less than a length and a width of the substrate, having inner contacts on a first side, and having second external contacts on a second side. The interposer is coupled to the second side of the substrate by one or more of the inner contacts. The assembly further comprises a second die disposed between the substrate and the interposer. The assembly further comprises first solder balls on the first external contacts, and second solder balls on the second external contacts. The first and second solder balls are configured to bond with co-planar package contacts. ## Claims ### Claim 1 A semiconductor device assembly, comprising: a substrate including a first plurality of external contacts at a lowermost surface of the substrate; an interposer having a length and a width each less than both a length and a width of the substrate, the interposer having a plurality of inner contacts on a first side and having a second plurality of external contacts on a second side opposite the first side, the interposer coupled to the lowermost surface of the substrate at least in part by one or more of the plurality of inner contacts; a die disposed between the lowermost surface of the substrate and the first side of the interposer; a first plurality of solder balls disposed on corresponding ones of the first plurality of external contacts; and a second plurality of solder balls disposed on corresponding ones of the second plurality of external contacts, wherein the first plurality of solder balls and the second plurality of solder balls are configured to bond with co-planar package contacts. ### Claim 2 (depends on 1) The semiconductor device assembly of claim 1, wherein each of the first plurality of solder balls has a first height and each of the second plurality of solder balls has a second height less than the first height. ### Claim 3 (depends on 1) The semiconductor device assembly of claim 1, wherein the first plurality of solder balls extends farther from the substrate than the second side of the interposer. ### Claim 4 (depends on 1) The semiconductor device assembly of claim 1, wherein the first plurality of solder balls and second plurality of solder balls together form a uniformly-spaced ball grid array (BGA). ### Claim 5 (depends on 1) The semiconductor device assembly of claim 1, wherein the die is electrically coupled to a plurality of chip attach pads on the substrate by direct chip attach (DCA). ### Claim 6 (depends on 1) The semiconductor device assembly of claim 1, wherein the die is electrically coupled to one or more of the plurality of inner contacts on the first side of the interposer. ### Claim 7 (depends on 1) The semiconductor device assembly of claim 1, wherein the substrate further includes a plurality of interposer contacts surrounded by the first plurality of external contacts, and wherein the interposer is electrically coupled to the substrate by interconnects corresponding to the plurality of interposer contacts. ### Claim 8 (depends on 7) The semiconductor device assembly of claim 7, wherein the second plurality of external contacts are electrically coupled to corresponding ones of the plurality of interposer contacts by one or more electrically conductive features extending at least partially through the interposer. ### Claim 9 (depends on 1) The semiconductor device assembly of claim 1, wherein the interposer further includes one or more thermal vias configured to conduct heat from the die through the interposer to one or more of the second plurality of external contacts. ### Claim 10 (depends on 1) The semiconductor device assembly of claim 1, wherein the die is adhered to the interposer by a thermal interface material. ### Claim 11 (depends on 1) The semiconductor device assembly of claim 1, further comprising a layer of underfill material between the interposer and the substrate, the layer of underfill material at least partially surrounding the die. ### Claim 12 (depends on 1) The semiconductor device assembly of claim 1, wherein the interposer comprises one of a printed circuit board, an organic substrate, a ceramic substrate, a metal lead frame, or a redistribution layer. ### Claim 13 (depends on 12) The semiconductor device assembly of claim 12, wherein the interposer comprises a redistribution layer in which the die is at least partially embedded. ### Claim 14 A method of forming a semiconductor device assembly, the method comprising: attaching a die to a lowermost surface of a substrate; attaching a front side of an interposer to the die and to the lowermost surface of the substrate; attaching a first plurality of solder balls to a first plurality of external contacts on the lowermost surface of the substrate; and attaching a second plurality of solder balls to a second plurality of external contacts on a back side of the interposer opposite the front side, wherein the first plurality of solder balls and the second plurality of solder balls are configured to bond with co-planar package contacts. ### Claim 15 (depends on 14) The method of claim 14, wherein attaching the die to the lowermost surface of the substrate comprises electrically coupling the die to a plurality of pads on the second side of the substrate by direct chip attach (DCA). ### Claim 16 (depends on 14) The method of claim 14, further comprising electrically coupling the die to one or more of a plurality of inner contacts on the font side of the interposer. ### Claim 17 (depends on 14) The method of claim 14, wherein the substrate further includes a plurality of interposer contacts on the lowermost surface of the substrate, and wherein attaching the front side of the interposer to the lowermost surface of the substrate comprises electrically coupling the interposer to the plurality of interposer contacts. ### Claim 18 (depends on 14) The method of claim 14, wherein attaching the front side of the interposer to the die comprises disposing a thermal interface material between the front side of the interposer and the die. ### Claim 19 (depends on 14) The method of claim 14, further comprising disposing a layer of underfill material between the interposer and the substrate, the layer of underfill material at least partially surrounding the die.