# US 12,191,279 B2 · Integrated circuit packages and methods of forming the same

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- Number: US 12,191,279 B2
- Document ID: US12191279B2
- Status: Granted
- Kind: B2
- Application number: 17/542,516
- Filed: 2021-12-06
- Published: 2022-03-24
- Granted: 2025-01-07
- Earliest claimed: 2019-07-23
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chen-Hua Yu; Kuo-Chung Yee
- Web page: https://patentgrep.com/patent/US12191279B2

## CPC

- H10P 72/74: {using temporarily an auxiliary support}
- H10W 90/00: Package configurations
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/685: comprising multiple insulating layers
- H10W 74/01: Manufacture or treatment
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10W 70/635: {Through-vias}
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit package includes a package structure including a plurality of first dies, a second redistribution structure, a second die and a second encapsulant. The package structure includes the first dies, a first encapsulant encapsulating the first dies, a first redistribution structure over the first encapsulant and a plurality of conductive pillars over the first redistribution structure. The second redistribution structure is disposed over the package structure, and electrically connected to the package structure through the conductive pillars. The second die is disposed between the conductive pillars and electrically connected to the second redistribution structure, wherein a first surface of the second die is substantially flush with a surface of the first redistribution structure and a second surface opposite to the first surface of the second die is substantially flush with a surface of the second redistribution structure. The second encapsulant encapsulates the conductive pillars and the second die.

## Claims

### Claim 1

An integrated circuit package, comprising:
a package structure, comprising a plurality of first dies, a first encapsulant encapsulating the first dies, a first redistribution structure over the first encapsulant and a plurality of conductive pillars over the first redistribution structure;
a second redistribution structure, disposed over the package structure, and electrically connected to the package structure through the conductive pillars;
a second die, disposed between the conductive pillars and electrically connected to the second redistribution structure, wherein a first surface of the second die is substantially flush with a surface of the first redistribution structure and a second surface opposite to the first surface of the second die is substantially flush with a surface of the second redistribution structure; and
a second encapsulant, encapsulating the conductive pillars and the second die, wherein the second die comprises a plurality of connectors electrically connected to the second redistribution structure, and the second encapsulant is disposed between the connectors.

### Claim 2 (depends on 1)

The integrated circuit package according to claim 1, wherein the second die is an integrated voltage regulator die or an integrated passive device die.

### Claim 3 (depends on 1)

The integrated circuit package according to claim 1, wherein the second die comprises a die attach film and is adhered to the first redistribution structure through the die attach film.

### Claim 4 (depends on 1)

The integrated circuit package according to claim 1, wherein the second die is disposed between two adjacent ones of the conductive pillars.

### Claim 5 (depends on 1)

The integrated circuit package according to claim 1, wherein the second encapsulant further encapsulates lateral sidewalls of the first redistribution structure and the first encapsulant.

### Claim 6 (depends on 1)

The integrated circuit package according to claim 1, wherein the second encapsulant further encapsulates a sidewall of the first redistribution structure and is disposed between the second die and one of the conductive pillars.

### Claim 7

An integrated circuit package, comprising:
a first redistribution structure and a second redistribution structure;
a semiconductor layer between the first redistribution structure and the second redistribution structure;
a plurality of conductive pillars disposed on the semiconductor layer and penetrating through the semiconductor layer, wherein the conductive pillars are disposed between and electrically connected to the first redistribution structure and the second redistribution structure; and
a first die, wherein the first die is disposed on the semiconductor layer between the first redistribution structure and the second redistribution structure.

### Claim 8 (depends on 7)

The integrated circuit package according to claim 7 further comprising a first encapsulant between the first redistribution structure and the second redistribution structure, wherein the first encapsulant encapsulates the conductive pillars and the first die.

### Claim 9 (depends on 8)

The integrated circuit package according to claim 8, wherein the first encapsulant further encapsulates sidewalls of the semiconductor layer and the first redistribution structure.

### Claim 10 (depends on 7)

The integrated circuit package according to claim 7, wherein sidewalls of the semiconductor layer are substantially flush with sidewalls of the first redistribution structure.

### Claim 11 (depends on 7)

The integrated circuit package according to claim 7, wherein a surface of the first die is substantially coplanar with surfaces of the conductive pillars and a surface of the second redistribution structure.

### Claim 12 (depends on 7)

The integrated circuit package according to claim 7 further comprising an adhesive layer between the first die and the semiconductor layer, wherein the first die is electrically connected to the first redistribution structure through the second redistribution structure and at least one of the conductive pillars.

### Claim 13 (depends on 7)

The integrated circuit package according to claim 7 further comprising a plurality of second dies and a first encapsulant encapsulating the second dies, wherein the first redistribution structure is disposed between the second dies and the semiconductor layer.

### Claim 14 (depends on 13)

The integrated circuit package according to claim 13, wherein sidewalls of the semiconductor layer are substantially flush with sidewalls of the first redistribution structure and the first encapsulant.

### Claim 15 (depends on 14)

The integrated circuit package according to claim 14 further comprising a second encapsulant encapsulating the conductive pillars, the first die, the semiconductor layer and the first encapsulant.

### Claim 16

A method of manufacturing an integrated circuit package, comprising:
forming a semiconductor layer on a first redistribution structure;
forming a plurality of conductive pillars in the semiconductor layer to electrically connect to the first redistribution structure;
forming a first die on the semiconductor layer between the conductive pillars; and
forming a second redistribution structure on the semiconductor layer to electrically connect to the first die and the conductive pillars.

### Claim 17 (depends on 16)

The method according to claim 16 further comprising forming a first encapsulant between the conductive pillars on the semiconductor layer.

### Claim 18 (depends on 17)

The method according to claim 17, wherein the first encapsulant further encapsulates the semiconductor layer and the first redistribution structure.

### Claim 19 (depends on 16)

The method according to claim 16, wherein the first die is disposed on the semiconductor layer through an adhesive layer.

### Claim 20 (depends on 16)

The method according to claim 16, wherein a surface of the first die is substantially coplanar with surfaces of the conductive pillars.