# US 12,191,273 B2 · Pre-molded leadframes in semiconductor devices

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- Number: US 12,191,273 B2
- Document ID: US12191273B2
- Status: Granted
- Kind: B2
- Application number: 17/210,380
- Filed: 2021-03-23
- Published: 2021-07-08
- Granted: 2025-01-07
- Earliest claimed: 2017-10-05
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Sreenivasan K. Koduri
- Web page: https://patentgrep.com/patent/US12191273B2

## CPC

- H10W 70/042: {Etching}
- H10W 70/40: Leadframes
- H10W 70/421: {Shapes or dispositions}
- H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)}
- H10W 70/435: {of insulating layers on leadframes, e.g. bridging members}
- H10W 70/458: {of insulating layers on leadframes}
- H10W 74/016: {using moulds}
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 70/415: {Leadframe inner leads serving as die pads}
- H10W 70/479: {on or in insulating or insulated package substrates, interposers, or redistribution layers}
- H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00}
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/01212: {at a different location than on the final device, e.g. forming solder preforms}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01255: {by using masks}
- H10W 72/019: {of bond pads}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/07252: {changes in structures or sizes}
- H10W 72/07253: {changes in shapes}
- H10W 72/07255: {changes in materials}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/232: {Plan-view shape, i.e. in top view}
- H10W 72/234: {Cross-sectional shape, i.e. in side view}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/251: {Materials}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/267: {Multiple bump connectors having different functions}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 95/00: Packaging processes not covered by the other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In one instance, a semiconductor package includes a metal leadframe having a first plurality of openings extending partially into the leadframe from the first side and a second plurality of openings extending partially into the leadframe from the second side together forming a plurality of leads. A pre-mold compound is positioned in the second plurality of openings that at least partially supports the plurality of leads. The semiconductor package has a plurality of bumps extending from the landing sites to a semiconductor die and a molding compounding at least partially covering the plurality of bumps and the metal leadframe. Other packages and methods are disclosed.

## Claims

### Claim 1

A semiconductor package comprising:
a semiconductor die including a plurality of bumps electrically connected to the semiconductor die;
a portion of a leadframe attached to the plurality of bumps, wherein the leadframe includes a first side and a second side opposing the first side, a first plurality of openings extending into the leadframe from the first side, and a second plurality of openings extending into the leadframe from the second side, the first plurality of openings including a first lateral width and the second plurality of openings including a second lateral width, wherein the second lateral width is greater than the first lateral width;
a first molding compound covering portions of the semiconductor die, the plurality of bumps and filling the first plurality of openings; and
a second molding compound filling the second plurality of openings; wherein each of the first plurality of openings is nonlinear in shape when viewed from a top view of the semiconductor package.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein each of the second plurality of openings is linear in shape when viewed from a bottom view of the semiconductor package.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein a width of some of the plurality of bumps is different than the others of the plurality of bumps.

### Claim 4 (depends on 1)

The semiconductor package of claim 1, wherein each of the plurality of bumps is tapered away from the leadframe along a longitudinal axis of each of the plurality of bumps.

### Claim 5 (depends on 1)

The semiconductor package of claim 1, wherein a depth of each the second plurality of openings is 50 to 80 percent of a height between the first side and the second side.

### Claim 6 (depends on 1)

The semiconductor package of claim 1, wherein the first plurality of openings is in a sinusoidal pattern.

### Claim 7 (depends on 1)

The semiconductor package of claim 1 further comprising at least two islands on the second mold compound.

### Claim 8 (depends on 7)

The semiconductor package of claim 7 further comprising a passive component attached to the at least two islands.

### Claim 9 (depends on 8)

The semiconductor package of claim 8, wherein the passive component includes one of a capacitor, inductor, and a current sensor.

### Claim 10 (depends on 8)

The semiconductor package of claim 8, wherein the at least two islands are supported by the second mold compound.

### Claim 11 (depends on 8)

The semiconductor package of claim 8, wherein the passive component is electrically connected to the semiconductor die via some of the plurality of bumps.

### Claim 12

A semiconductor package comprising:
a metal leadframe having a first side and a second side, wherein the second side is opposed to the first side, the metal leadframe comprising:
a first plurality of openings extending partially into the leadframe from the first side, the first plurality of openings having a lateral width W1,
a second plurality of openings extending partially into the leadframe from the second side, the second plurality of openings having a lateral width W2 that is greater than the width W1, wherein the first plurality of openings intersect the second plurality of openings to form a plurality of leads on the leadframe,
an insulating material positioned in the second plurality of openings, wherein the insulating material at least partially supports the plurality of leads, and
a plurality of landing sites on the first side of the leadframe between the first plurality of openings;
a plurality of bumps extending from the landing sites to a semiconductor die; and
a molding compounding at least partially covering the plurality of bumps and the metal leadframe; wherein each of the plurality of bumps is tapered away from the leadframe along a longitudinal axis of each of the plurality of bumps.

### Claim 13 (depends on 12)

The package of claim 12, wherein the insulating material substantially fills the second plurality of openings.

### Claim 14 (depends on 12)

The package of claim 12, wherein each of the first plurality of openings is non-linear in shape when viewed from a top view of the semiconductor package, and wherein each of the second plurality of openings is linear in shape when viewed from a bottom view of the semiconductor package.

### Claim 15 (depends on 14)

The package of claim 14, wherein some of the plurality of bumps overlap others of the plurality of bumps when viewed from the top view of the semiconductor package.

### Claim 16 (depends on 12)

The package of claim 12, wherein a depth D2 of the second plurality of openings is fifty to eighty percent of a depth D3 of the metal leadframe, wherein in D3 is a distance from the first side of the leadframe to the second side of the leadframe.

### Claim 17 (depends on 12)

The package of claim 12, wherein the first plurality of openings and the second plurality of openings are aligned to fully separate portions of the leadframe.