# US 12,191,271 B2 · Semiconductor structure comprising up-narrow and down-wide openings and forming method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,191,271 B2 - Document ID: US12191271B2 - Status: Granted - Kind: B2 - Application number: 17/661,375 - Filed: 2022-04-29 - Published: 2023-07-13 - Granted: 2025-01-07 - Earliest claimed: 2022-01-07 - Assignees: Changxin Memory Technologies, Inc. - Applicants: Changxin Memory Technologies, Inc. - Inventors: Zengyan Fan - Web page: https://patentgrep.com/patent/US12191271B2 ## CPC - H10W 72/072: {of bump connectors} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/012: {of bump connectors, dummy bumps or thermal bumps} - H10W 72/019: {of bond pads} - H10W 72/071: {Connecting or disconnecting} - H10W 72/07232: {Compression bonding, e.g. thermocompression bonding} - H10W 72/90: Bond pads, in general - H10W 72/01255: {by using masks} - H10W 72/01904: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates} - H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/247: {Dispositions of multiple bumps} - H10W 72/9445: {Top-view layouts, e.g. mirror arrays} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract The present application provides a semiconductor structure and a forming method thereof. The method of forming the semiconductor structure includes: providing a semiconductor chip and a substrate; forming, on the substrate, a first covering film covering a metal pad and a surface of the substrate, a plurality of up-narrow and down-wide openings being formed in the first covering film, and a bottom of each of the up-narrow and down-wide openings correspondingly exposing a surface of the metal pad; and flipping the semiconductor chip onto the substrate, such that a solder bump on a metal pillar is correspondingly located in the up-narrow and down-wide opening, and the solder bump fill the up-narrow and down-wide opening. ## Claims ### Claim 1 A method of forming a semiconductor structure, comprising: providing a semiconductor chip, a plurality of protruded metal pillars and a solder bump on a top surface of each of the plurality of protruded metal pillars being formed on the semiconductor chip; providing a substrate, a plurality of metal pads being formed on a surface of the substrate; forming, on the substrate, a first covering film covering the plurality of metal pads and the surface of the substrate, a plurality of up-narrow and down-wide openings being formed in the first covering film, and a bottom of each of the plurality of up-narrow and down-wide openings correspondingly exposing a surface of the plurality of metal pads; and flipping the semiconductor chip onto the substrate, such that the solder bump on each of the plurality of protruded metal pillars is correspondingly located in the plurality of up-narrow and down-wide openings through the first covering film, and the solder bump fills a corresponding one of the plurality of up-narrow and down-wide openings inside with an up-narrow and down-wide shape. ### Claim 2 (depends on 1) The method of forming the semiconductor structure according to claim 1, wherein the plurality of up-narrow and down-wide openings comprises a first opening and a second opening that communicate with each other, the second opening is located on the first opening, and a width of the second opening is smaller than a width of the first opening. ### Claim 3 (depends on 2) The method of forming the semiconductor structure according to claim 2, wherein the first covering film is a negative photoresist film. ### Claim 4 (depends on 3) The method of forming the semiconductor structure according to claim 3, wherein a process for forming the plurality of up-narrow and down-wide openings in the first covering film comprises: forming, on the substrate, the negative photoresist film covering the plurality of metal pads and the surface of the substrate; performing exposure on the negative photoresist film, wherein during the exposure, a part of the negative photoresist film directly over the plurality of metal pads is not exposed, a part of the negative photoresist film over a peripheral edge region of the plurality of metal pads is half exposed, and the remaining negative photoresist film is fully exposed; and developing the negative photoresist film upon the exposure, removing the unexposed negative photoresist film, and forming the plurality of up-narrow and down-wide openings in the remaining negative photoresist film. ### Claim 5 (depends on 2) The method of forming the semiconductor structure according to claim 2, wherein the first covering film comprises a first film layer covering the plurality of metal pads and the surface of the substrate and a second film layer on the first film layer, and a material of the first film layer is different from a material of the second film layer. ### Claim 6 (depends on 5) The method of forming the semiconductor structure according to claim 5, wherein a process for forming the plurality of up-narrow and down-wide openings in the first covering film comprises: forming the first film layer covering the plurality of metal pads and the surface of the substrate; forming the second film layer on the first film layer; etching the second film layer with anisotropic dry etching to form the second opening in the second film layer, a bottom of the second opening exposing a part of a surface of the first film layer; and etching, with an isotropic wet etching along the second opening, the first film layer on the bottom of the second opening to form the first opening in the first film layer, a width of the first opening being greater than a width of the second opening. ### Claim 7 (depends on 1) The method of forming the semiconductor structure according to claim 1, wherein a second covering film covering the plurality of protruded metal pillars and the solder bump on the top surface of each of the plurality of protruded metal pillars is further provided on the semiconductor chip. ### Claim 8 (depends on 7) The method of forming the semiconductor structure according to claim 7, wherein a material of the second covering film is a non-conductive film. ### Claim 9 (depends on 8) The method of forming the semiconductor structure according to claim 8, wherein after the semiconductor chip is flipped onto the substrate, a thermo compression bonding is employed to ensure that the solder bump on each of the plurality of protruded metal pillars is correspondingly located in the plurality of up-narrow and down-wide openings through the first covering film, and the solder bump fills the corresponding one of the plurality of up-narrow and down-wide openings. ### Claim 10 (depends on 9) The method of forming the semiconductor structure according to claim 9, wherein the thermo compression bonding comprises: clamping the semiconductor chip with a clamping head and performing a first heating on the semiconductor chip, such that the second covering film is molten, and the solder bump on each of the plurality of protruded metal pillars is correspondingly located in the plurality of up-narrow and down-wide openings through the first covering film; and performing a second heating on the semiconductor chip through the clamping head, such that the solder bump is molten to fill the corresponding one of the plurality of up-narrow and down-wide openings, a temperature of the second heating being greater than a temperature of the first heating. ### Claim 11 (depends on 10) The method of forming the semiconductor structure according to claim 10, wherein the thermo compression bonding is performed at a pressure of 5-12 N for 3-5 s, the first heating is performed at a temperature of 60-70° C., and the second heating is performed at a temperature of 220-250° C. ### Claim 12 (depends on 1) The method of forming the semiconductor structure according to claim 1, wherein the substrate comprises a front side and a back side opposite to the front side, the plurality of metal pads are formed on the front side of the substrate, and a plurality of external pads are formed on the back side of the substrate. ### Claim 13 (depends on 12) The method of forming the semiconductor structure according to claim 12, wherein a process for forming the plurality of metal pads and the plurality of external pads comprises: forming a metal layer on a surface of the front side and a surface of the back side of the substrate; forming a dry film on a surface of the metal layer on the front side and the back side of the substrate; exposing and developing the dry film, such that a first opening exposing a part of the surface of the metal layer on the front side of the substrate is formed in the dry film on the front side, and a second opening exposing a part of the surface of the metal layer on the back side of the substrate is formed in the dry film on the back side; and removing the exposed metal layer along the first opening and the second opening, thus forming the plurality of metal pads on the front side of the substrate and the plurality of external pads on the back side of the substrate. ### Claim 14 A semiconductor structure, comprising: a semiconductor chip, a plurality of protruded metal pillars and a solder bump on a top surface of each of the plurality of protruded metal pillars being formed on the semiconductor chip; a substrate, a plurality of metal pads being formed on a surface of the substrate; and a first covering film located on the substrate and covering the plurality of metal pads and the surface of the substrate, a plurality of up-narrow and down-wide openings being formed in the first covering film, and a bottom of each of the plurality of up-narrow and down-wide openings correspondingly exposing a surface of the plurality of metal pads, wherein the semiconductor chip is flipped onto the substrate, such that the solder bump on each of the plurality of protruded metal pillars is correspondingly located in the plurality of up-narrow and down-wide openings, and fills a corresponding one of the plurality of up-narrow and down-wide openings inside with an up-narrow and down-wide shape. ### Claim 15 (depends on 14) The semiconductor structure according to claim 14, wherein the plurality of up-narrow and down-wide openings comprises a first opening and a second opening that communicate with each other, the second opening is located on the first opening, and a width of the second opening is smaller than a width of the first opening. ### Claim 16 (depends on 15) The semiconductor structure according to claim 15, wherein the width of the second opening is ⅕-½ of the width of the first opening. ### Claim 17 (depends on 15) The semiconductor structure according to claim 15, wherein the first covering film is a negative photoresist film; wherein the first covering film comprises a first film layer covering the plurality of metal pads and the surface of the substrate and a second film layer on the first film layer, a material of the first film layer is different from a material of the second film layer, the first opening is located in the first film layer, and the second opening is located in the second film layer. ### Claim 18 (depends on 14) The semiconductor structure according to claim 14, wherein a second covering film covering the plurality of protruded metal pillars is further provided between the semiconductor chip and the substrate. ### Claim 19 (depends on 18) The semiconductor structure according to claim 18, wherein a material of the second covering film is a non-conductive film. ### Claim 20 (depends on 14) The semiconductor structure according to claim 14, wherein the substrate comprises a front side and a back side opposite to the front side, the plurality of metal pads are formed on the front side of the substrate, and a plurality of external pads are formed on the back side of the substrate.