# US 12,191,269 B2 · Three-dimensional memory device and method for forming the same

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- Number: US 12,191,269 B2
- Document ID: US12191269B2
- Status: Granted
- Kind: B2
- Application number: 17/483,121
- Filed: 2021-09-23
- Published: 2023-01-05
- Granted: 2025-01-07
- Earliest claimed: 2021-06-30
- Assignees: Yangtze Memory Technologies Co., Ltd.
- Applicants: Yangtze Memory Technologies Co., Ltd.
- Inventors: Yuancheng Yang; Wenxi Zhou; Zhiliang Xia; Wei Liu
- Web page: https://patentgrep.com/patent/US12191269B2

## CPC

- H10W 90/00: Package configurations
- H10B 43/40: characterised by the peripheral circuit region
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0253: {comprising forming the through-semiconductor vias after stacking of the chips, wafers or substrates}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 20/4421: {the principal metal being copper}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10W 72/01: {Manufacture or treatment}
- H10W 80/033: {by chemical means, e.g. etching}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A three-dimensional (3D) memory device includes a first semiconductor structure and a second semiconductor structure. A first semiconductor structure includes a first substrate, and a memory array structure disposed on the first substrate. The second semiconductor structure is disposed over the first semiconductor structure, and the second semiconductor structure includes a second substrate, and a peripheral device in contact with the second substrate. The second substrate is formed between the peripheral device and the first semiconductor structure.

## Claims

### Claim 1

A three-dimensional (3D) memory device, comprising:
a first semiconductor structure comprising a first semiconductor layer, and a memory array structure disposed on the first semiconductor layer; and
a second semiconductor structure disposed over the first semiconductor structure, the second semiconductor structure comprising a second semiconductor layer, and a peripheral device in contact with the second semiconductor layer,
wherein the second semiconductor layer is formed between the peripheral device and the first semiconductor structure;
wherein a contact pad for transferring electrical signals between the 3D memory device and external circuits is formed on the second semiconductor structure opposite to the second semiconductor layer; and
wherein a first through silicon contact structure penetrates through the second semiconductor layer to the first semiconductor structure, and the first semiconductor layer is electrically coupled to the peripheral device through the first through silicon contact structure.

### Claim 2 (depends on 1)

The 3D memory device of claim 1, further comprising:
an interconnection layer disposed over the second semiconductor structure,
wherein the memory array structure is disposed between the interconnection layer and the first semiconductor layer; and
a contact pad of the interconnection layer is electrically coupled to the peripheral device.

### Claim 3 (depends on 1)

The 3D memory device of claim 1, further comprising:
an interconnection layer disposed over the first semiconductor structure,
wherein the second semiconductor layer is disposed between the interconnection layer and the peripheral device; and
a contact pad of the interconnection layer is electrically coupled to the peripheral device.

### Claim 4 (depends on 1)

The 3D memory device of claim 1, wherein the memory array structure further comprises:
a memory stack having a plurality of interleaved conductive layers and dielectric layers; and
a channel structure extending through the memory stack, the channel structure comprising a memory film and a semiconductor channel,
wherein the semiconductor channel is in contact with the first semiconductor layer.

### Claim 5 (depends on 2)

The 3D memory device of claim 2, wherein the peripheral device further comprises a transistor, and the first semiconductor layer is electrically coupled to a first source/drain terminal of the transistor through the first through silicon contact structure.

### Claim 6 (depends on 5)

The 3D memory device of claim 5, wherein the contact pad is electrically coupled to a second source/drain terminal of the transistor.

### Claim 7 (depends on 6)

The 3D memory device of claim 6, further comprising a second through silicon contact structure penetrating through the second semiconductor layer, and the memory array structure is electrically coupled to the peripheral device through the second through silicon contact structure.

### Claim 8 (depends on 7)

The 3D memory device of claim 7, wherein the first through silicon contact structure, the second through silicon contact structure, and the interconnection layer are formed by copper (Cu).

### Claim 9 (depends on 1)

The 3D memory device of claim 1, further comprising a bonding interface between the first semiconductor structure and the second semiconductor structure.

### Claim 10 (depends on 1)

The 3D memory device of claim 1, wherein the first semiconductor layer comprises single crystalline silicon layer.

### Claim 11 (depends on 10)

The 3D memory device of claim 10, wherein the second semiconductor layer comprises single crystalline silicon layer.

### Claim 12

A method for forming a three-dimensional (3D) memory device, comprising:
forming a memory array structure over a first semiconductor layer;
forming a second semiconductor layer over the memory array structure;
after forming the second semiconductor layer over the memory array structure, forming a peripheral device in contact with the second semiconductor layer; and
forming an interconnection layer over the peripheral device,
wherein the second semiconductor layer is disposed between the peripheral device and the memory array structure.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
forming a contact pad embedded within the interconnection layer, wherein the contact pad is in contact with the peripheral device.

### Claim 14 (depends on 12)

The method of claim 12, further comprising:
forming a contact pad over the first semiconductor layer, wherein the first semiconductor layer is disposed between the contact pad and the memory array structure.

### Claim 15 (depends on 12)

The method of claim 12, wherein forming the second semiconductor layer over the memory array structure, further comprises:
providing a third semiconductor layer comprising a dielectric layer;
bonding the third semiconductor layer to the memory array structure in a face-to-face manner through the dielectric layer;
forming a heterogeneous interface in the third semiconductor layer; and
removing a portion of the third semiconductor layer along the heterogeneous interface to form the second semiconductor layer.

### Claim 16 (depends on 12)

The method of claim 12, wherein forming the second semiconductor layer over the memory array structure, further comprises:
bonding a composite semiconductor layer on the memory array structure; and
removing a portion of the composite semiconductor layer to form the second semiconductor layer.

### Claim 17

A method for forming a three-dimensional (3D) memory device, comprising:
forming a first dielectric layer over a first semiconductor layer;
forming a memory array structure in the first dielectric layer;
bonding a second semiconductor layer to the first dielectric layer, wherein the second semiconductor layer comprises a second dielectric layer, and the second dielectric layer is bonded to the first dielectric layer;
forming a heterogeneous interface in the second semiconductor layer;
removing a portion of the second semiconductor layer along the heterogeneous interface to form a third semiconductor layer over the memory array structure;
forming a peripheral device in the third semiconductor layer; and
forming an interconnection layer over the peripheral device,
wherein the third semiconductor layer is disposed between the peripheral device and the memory array structure.

### Claim 18 (depends on 17)

The method of claim 17, wherein forming the heterogeneous interface in the second semiconductor layer comprises implanting a dopant into the second semiconductor layer.

### Claim 19 (depends on 17)

The method of claim 17, further comprising:
forming a first through silicon contact structure penetrating the third semiconductor layer,
wherein the peripheral device is electrically coupled to the first semiconductor layer through the first through silicon contact structure.

### Claim 20 (depends on 1)

The 3D memory device of claim 1, wherein the first through silicon contact structure extends in the second semiconductor structure to the first semiconductor structure.